Juniper open-register-design-tool issues

Juniper / open-register-design-tool

Tool to generate register RTL, models, and docs using SystemRDL or JSpec input

Apache License 2.0

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issues

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build fixes

#96 sdnellen closed 2 weeks ago
0
added rdl example replicating ext rf and addrmaps

#95 sdnellen closed 1 month ago
0
Solving decoding congestion

#94 ehudeliaz opened 1 month ago
3
Merge of sdnellen fork

#93 sdnellen closed 1 year ago
0
add ordt/work/makefile

#92 lpfzero closed 2 years ago
0
How to dump JSON file from a rdl?

#91 EngRaff92 opened 2 years ago
0
Generate C header file

#90 prdwivedi closed 1 year ago
1
Build in Debian/testing does not work

#89 wzab opened 3 years ago
1
Struct Generation not working

#88 abagchi opened 3 years ago
0
Sticky interrupt with hardware precedence and write-one-to-clear can not be cleared

#87 tenaliram opened 3 years ago
0
Use assignment delay parameter in SyncStage

#86 avi-jois closed 1 year ago
0
addressing and alignment properties of addressmap not being followed

#85 tenaliram opened 4 years ago
1
Control bit-width of address bus in addrmap

#84 tenaliram opened 4 years ago
2
Cannot get Ordt-viewer to work

#83 jyaghutiel opened 4 years ago
0
clock gating issue

#82 xinhui-zhang opened 4 years ago
0
When there is a secondary processor, decoder logic is out of sync.

#81 kongty opened 4 years ago
0
Is there an option to enable address channel for each write and read, instead of one address channel?

#80 kongty opened 4 years ago
0
How to have holding registers

#79 tkafafi opened 4 years ago
0
External Reset signals Causing RTL generation to fail

#78 neenuprince opened 4 years ago
2
ORDT coverpoints in RTL does not rename the resets to the system reset

#77 neenuprince closed 4 years ago
4
gererate register verilog module has synthesis error when use Synopsys DC

#76 zhajio1988 closed 4 years ago
5
Is there an option to enable or disable the flopping of inputs and/or outputs to the RTL generated?

#75 neenuprince opened 5 years ago
1
"gated_logic_access_delay" affects access delay even if clock gating disabled

#74 roowatt closed 5 years ago
2
How to connect the APB bus to the generated verilog module？

#73 zhajio1988 opened 5 years ago
3
how to write addrmap block?

#72 zhajio1988 closed 5 years ago
4
New commits will be made to the sdnellen fork

#71 sdnellen opened 5 years ago
0
RTl code has floating signals for HWRead SWwrite registers causing X's

#70 neenuprince opened 5 years ago
2
Register field ordering is broken.

#69 sjalloq opened 5 years ago
2
Ordt should generate an error on { sw=rw; hw=w; } with no hw we.

#68 sjalloq opened 5 years ago
1
Interrupt enable definitions are not obeyed

#67 sjalloq closed 5 years ago
5
Reset terms are not the correct width

#66 sjalloq closed 5 years ago
2
Unused wires generated

#65 sjalloq closed 5 years ago
2
Bug: adding a reset signal breaks ordt

#64 sjalloq closed 5 years ago
4
Build error from source

#63 sjalloq opened 5 years ago
2
Incomplete reset specification on external register interface

#62 petenixon opened 5 years ago
5
Registers with intr attribute and bothedge and negedge not reseting properly

#61 kdloe closed 5 years ago
4
Add context to create() calls for UVM registers

#60 ebertland closed 5 years ago
0
some External interface signals are not being reset

#59 neenuprince closed 5 years ago
2
Code generated by "resetsignal" attribute not proper

#58 neenuprince closed 5 years ago
3
Internal error accessing SystemVerilogDefinedSignalMap generating UVM output

#57 ebertland closed 5 years ago
5
Support for "sharedextbus" and "errextbus"

#56 kdloe closed 5 years ago
4
Requesting clarification on async attribute vs use_async_resets param

#55 kdloe closed 5 years ago
1
Non-synthesizable "#1" in generated rtl

#54 kdloe closed 5 years ago
6
Default bit ordering on reg fields

#53 natcoro closed 5 years ago
2
XML Data Dictionary

#52 WebMonkey007 opened 5 years ago
2
Feature Request: Function to get register name

#51 kprabhu36 closed 5 years ago
4
Feature Request : There is no way to generate the c++ driver with more than two RDL files

#50 kprabhu36 closed 6 years ago
3
Using native uvm classes without extended classes

#49 Bobbyq66 closed 6 years ago
4
param min_data_size seems to be interpreted as the default register size for SystemRDL

#48 amykyta3 closed 6 years ago
2
RDL UDP in top-level component is silently dropped in XML output

#47 amykyta3 closed 6 years ago
2