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SymbiFlow
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yosys
SymbiFlow WIP changes for Yosys Open SYnthesis Suite
http://www.clifford.at/yosys/
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Fix inference of 3-state buffers
#45
mkurc-ant
closed
4 years ago
1
WIP: Initial version of the xdc plugin support
#44
tmichalak
closed
4 years ago
2
Current delta between SymbiFlow/yosys and YosysHQ/Yosys in master+wip
#43
mithro
opened
4 years ago
1
attributes-on-parameters branch currently broken
#42
mithro
opened
4 years ago
4
[Branch] attributes-on-parameters
#41
mithro
opened
4 years ago
5
[Branch] carry-rework
#40
mithro
opened
4 years ago
4
[Branch] disable-ramb36e1
#39
mithro
opened
4 years ago
0
[Branch] disable-srl16
#38
mithro
opened
4 years ago
2
Add SRLC16E primitive.
#37
mkurc-ant
closed
4 years ago
6
Disable SRL16 until VPR/xc7 supports it.
#36
litghost
closed
4 years ago
0
Ensure that important RAM modes are exposed to Yosys
#35
litghost
opened
5 years ago
0
[pull] master from YosysHQ:master
#34
pull[bot]
closed
4 years ago
0
add RAM32X1D inference
#33
HackerFoo
closed
4 years ago
0
Add 8/16/32 bit widths for block RAM inference
#32
HackerFoo
opened
5 years ago
7
enable inference for RAMB36E1
#31
HackerFoo
closed
4 years ago
8
Support for attributes on port connections
#30
mkurc-ant
closed
5 years ago
3
Dedicated top of carry pin is sourced from O[Y_WIDTH].
#29
litghost
closed
5 years ago
1
Update CARRY4 sim model to handle disconnected CIN signal.
#28
litghost
closed
5 years ago
2
Full support for attributes in Yosys
#27
mkurc-ant
opened
5 years ago
5
Add carry chain spill back to synthesis.
#26
litghost
closed
5 years ago
0
Support for attributes on parameters in Verilog
#25
mkurc-ant
closed
5 years ago
11
Sync master+wip with upstream
#24
mkurc-ant
closed
5 years ago
0
Use CARRY4 (with an explicit COUT) instead of CARRY0/CARRY.
#23
litghost
closed
5 years ago
1
Better integration with BROWN-Yosys-ABC
#22
XVilka
opened
5 years ago
0
Sync master+wip with upstream
#21
litghost
closed
5 years ago
0
Sync master with upstream master
#20
litghost
closed
5 years ago
0
Request for integration with YosysHQ master branch
#19
mkurc-ant
closed
5 years ago
0
Update master to upstream master
#18
litghost
closed
5 years ago
0
Yosys cannot infer BRAM correctly on current master+wip
#17
mkurc-ant
closed
5 years ago
5
Temporarily disable RAMB36 synthesis.
#16
litghost
closed
5 years ago
1
Merge yosyshq/master back into master+wip.
#15
litghost
closed
5 years ago
0
Merge upstream patches downstream
#14
litghost
closed
5 years ago
0
merge "YosysHQ/yosys" into master+wip
#13
elms
closed
5 years ago
0
Sync with YosysHQ
#12
litghost
closed
5 years ago
0
Disable RAM32x1D synthesis
#11
litghost
closed
5 years ago
0
Merge WREDUCE fix to Symbiflow branch
#10
litghost
closed
5 years ago
0
Update yosys with setundef
#9
litghost
closed
5 years ago
1
Moved techmaps from Yosys to SymbiFlow
#8
mkurc-ant
closed
5 years ago
0
Edif array order fix
#7
mkurc-ant
closed
5 years ago
4
Correct map entries for some FF's
#6
litghost
closed
5 years ago
1
Changes to support 7-series VPR flow
#5
litghost
closed
5 years ago
7
Update SymbiFlow/yosys/master to YosysHq/yosys/master
#4
litghost
closed
5 years ago
0
Update SymbiFlow/yosys to YosysHQ/yosys
#3
litghost
closed
5 years ago
0
Working 7-series carry chains on VPR
#2
litghost
closed
5 years ago
0
Xilinx VPR start-up
#1
litghost
closed
5 years ago
0
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