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angr
/
vex
A patched version of VEX to work with PyVEX.
GNU General Public License v2.0
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Add auxprogs/genoffsets.dSYM to .gitignore
#60
twizmwazin
closed
8 months ago
0
guest_amd64_spechelper: Fix size inconsistency for ADDL CondZ.
#59
ltfish
closed
8 months ago
2
support RISC-V 64 in `libvex_basictype.h`
#58
moui0
closed
9 months ago
1
Pr/draper riscv patch2
#57
EvelynVusky
closed
11 months ago
0
VEX IR generator added for RISCV WFI instruction
#56
EvelynVusky
closed
11 months ago
7
Add Build workflow
#55
twizmwazin
closed
1 year ago
0
Add RISCV64 support
#54
alikates
closed
1 year ago
8
Feat/amd64 retf
#53
dannyp303
closed
1 year ago
2
API Calls representation in VEX
#52
nav60
opened
1 year ago
9
amd64: segment register read/write
#51
rhelmot
closed
1 year ago
0
Spechelper for FP compares
#50
udiboy1209
opened
1 year ago
1
AMD64: Support rdsspd/rdsspq.
#49
ltfish
closed
2 years ago
0
Getting the exact registers in ARM 32-bit
#48
spencerwuwu
closed
2 years ago
2
AMD64: Add a spechelper for ADDL and CondZ.
#47
ltfish
closed
2 years ago
0
ARM: Support sub.w reg, reg, reg, lsl #0-4.
#46
ltfish
closed
2 years ago
0
ARM: Add spechelpers for ADD-EQ/NE.
#45
ltfish
closed
2 years ago
0
Opt: Do not disable optimizations of VEX-specific registers.
#44
ltfish
closed
2 years ago
0
Support lifting ARM syscalls under OABI.
#43
degrigis
closed
2 years ago
0
Don't truncate 64-bit segment base in 32-bit addressing mode.
#42
edmcman
closed
2 years ago
5
possible vex bug in handling segment offsets
#41
hammerpig
closed
2 years ago
4
Provide explicit amount of lookback information to vex
#40
rhelmot
closed
3 years ago
0
Windows make build patch
#39
TACIXAT
closed
1 year ago
3
[WIP] amd64_toIR: Decode endbr.
#38
ltfish
closed
3 years ago
0
Add support for GCC 10
#37
h313
closed
4 years ago
1
`libvex_guest_offsets.h` not found when pip install -e .\pyvex
#36
yifanwww
closed
4 years ago
0
Opt: Support disabling cross-instruction optimizations.
#35
ltfish
closed
4 years ago
0
MSVC Compatibility
#34
ltfish
closed
4 years ago
0
Add ijk_privileged jumpkind, use it for cli/sti
#33
rhelmot
closed
4 years ago
0
[WIP] AMD64: Support lifting cmpsb.
#32
ltfish
opened
4 years ago
0
Add support for ADCX/ADOX instructions
#31
zx2c4
closed
4 years ago
1
ARM: Support decoding semihosting (svc 0x123456).
#30
ltfish
closed
4 years ago
0
Implement strict_block_end for loop, jrcxz, jecxz on AMD64.
#29
ltfish
closed
4 years ago
0
Manually select `ar` on macOS so pyvex builds
#28
Maximus-
closed
4 years ago
1
adding support for mov instructions having control registers
#27
r00tus3r
closed
4 years ago
0
s390x: allow lifting of vector instructions
#26
mephi42
closed
4 years ago
7
s390x: update to upstream revision 7e9113cb7
#25
mephi42
closed
4 years ago
10
ARM: Mark LDMFD SP, {xxx, SP, PC} as a return instruction.
#24
ltfish
closed
5 years ago
0
`ld x86_64 error` under mac os mojave (10.14+) with darwin kernel 18+
#23
FFengIll
closed
4 years ago
4
Per the docs, PC used in ADR should have a +4 added
#22
subwire
opened
5 years ago
1
s390 EXLR will probably segfault if target is outside the current segment
#21
rhelmot
opened
5 years ago
1
s390x: handle EXRL when its target is in the same buffer
#20
mephi42
closed
5 years ago
0
Allow analyzing s390x on little-endian hosts
#19
mephi42
closed
5 years ago
5
Allow analyzing s390x on little-endian hosts
#18
mephi42
closed
5 years ago
1
fix early initialization of s390_host_hwcaps in LibVEX_FrontEnd
#17
mephi42
closed
5 years ago
2
ARM: Mark LDMDB R11, {xxx, pc} as a return instruction.
#16
ltfish
closed
6 years ago
0
Fix CB{N}Z thumb instruction second attempt
#15
ArtemShypotilov
closed
6 years ago
1
Build breakage on non-x86 due to -malign-double
#14
afaerber
closed
6 years ago
4
Changed jumpkind for LDR PC, [SP],#4 thumb mode instruction
#13
ArtemShypotilov
closed
6 years ago
1
Added translation for instruction LDRSW (literal).
#12
phros
closed
6 years ago
4
New Instructions for VEX?
#11
AndyXan
closed
6 years ago
8
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