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chipsalliance
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Cores-VeeR-EL2
VeeR EL2 Core
https://chipsalliance.github.io/Cores-VeeR-EL2/html/main/docs_rendered/html/index.html
Apache License 2.0
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Add user mode chapter to documentation
#216
mczyz-antmicro
closed
3 days ago
1
Apply fixes after merging changes from caliptra-rtl
#215
kiryk
opened
4 days ago
5
Add PMP chapter to documentation
#214
mczyz-antmicro
closed
4 days ago
2
Detect Verilator version and supply proper flags for tools/riscv-dv
#213
rickliu2000
opened
5 days ago
2
Change coverage report structure
#212
jbylicki
opened
6 days ago
1
Add OpenOCD test
#211
RRozak
opened
6 days ago
4
Fix spelling errors and headings in documentation
#210
mczyz-antmicro
closed
6 days ago
1
Add tests for ECC
#209
robertszczepanski
opened
6 days ago
2
build riscv-dv test with both u-mode enabled and disabled
#208
wsipak
opened
1 week ago
4
Extend coverage tests
#207
kiryk
opened
1 week ago
8
[Don't merge] Add dat files to artifacts
#206
koblonczek
opened
1 week ago
0
tools/riscv-dv: fix failing PMP tests
#205
fkokosinski
closed
1 week ago
3
resize iccm ecc signals
#204
wsipak
opened
2 weeks ago
3
remove verible formatter
#203
wsipak
closed
1 week ago
1
Include source code in the dashboard
#202
RRozak
opened
2 weeks ago
2
[DNM] tools/riscv-dv: add bitmanip tests
#201
fkokosinski
opened
2 weeks ago
3
WIP: Extend coverage tests
#200
kiryk
closed
4 days ago
2
tools/riscv-dv: add more PMP tests
#199
fkokosinski
closed
1 week ago
3
Render docs in Github Pages
#198
jbylicki
closed
1 week ago
10
test specifying privilege modes in simulation in riscv-dv
#197
wsipak
opened
3 weeks ago
3
WIP: Fix linter warnings related to undriven nets
#196
koblonczek
opened
3 weeks ago
2
Test instruction buffer debug override
#195
koblonczek
opened
3 weeks ago
3
Testbench: Fix connections between core and memories
#194
kiryk
closed
1 month ago
2
tools/riscv-dv: add more PMP tests
#193
fkokosinski
closed
2 weeks ago
15
Prepare for user mode tests
#192
kiryk
opened
1 month ago
0
Fix Verilator build
#191
RRozak
closed
1 month ago
2
Remove unused jtag module files
#190
RRozak
closed
1 month ago
2
Upload artifacts only once
#189
RRozak
closed
1 month ago
3
Enable lib_ahb_to_axi4 tests
#188
RRozak
closed
1 month ago
1
User mode support
#187
mkurc-ant
closed
2 weeks ago
4
Fix constant name in custom veer config for riscv-dv
#186
tmichalak
closed
1 month ago
1
add a test for user mode
#185
wsipak
opened
1 month ago
10
CI: Add more files to cache hash calculation
#184
kiryk
closed
1 month ago
3
CI: Add testlists.yaml to cache hash calculation
#183
tmichalak
closed
1 month ago
2
Sync code with caliptra-rtl repo
#182
koblonczek
closed
2 weeks ago
2
Show only design dir in the dashboard and enable 'all' coverage in all tests
#181
RRozak
closed
1 month ago
5
Add tests of zbs and zbb instructions
#180
RRozak
closed
1 month ago
2
Increase AXI timeout to prevent spontaneous DMA test failures
#179
koblonczek
closed
1 month ago
1
Fix black and isort not failing CI on incorrect formatting
#178
koblonczek
closed
1 month ago
1
Add tests of pack and packh instructions
#177
RRozak
closed
1 month ago
2
tools/riscv-dv: add a separate testlist.yaml
#176
fkokosinski
closed
1 month ago
6
Add tests of sh??add instructions
#175
RRozak
closed
1 month ago
3
Non-functional fixes to exu_alu testbench
#174
RRozak
closed
1 month ago
2
Use C++14
#173
kiryk
closed
1 month ago
0
Add .dat files to artifacts
#172
RRozak
closed
1 month ago
3
Enable all coverage in all tests
#171
RRozak
closed
1 month ago
2
Add Test-Microarchitectural to Report-Coverage dependencies
#170
RRozak
closed
1 month ago
2
EL2_DMA_CTRL.sv AXI interface the burst length mode, awlen & arlen is not used, it is Error ?
#169
xiaolei-cheng
opened
2 months ago
0
Relation between Core reset(rst_l) and dbg_rst_l
#168
Syed-mudabbir-ahsan
opened
2 months ago
0
Bump Verilator for UVM tests
#167
kbieganski
closed
3 months ago
1
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