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chipsalliance
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riscv-vector-tests
Unit tests generator for RVV 1.0
Apache License 2.0
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Dont write fcsr for test w/ fp
#53
sequencer
opened
2 weeks ago
0
build all fault
#52
chenyuanyping
closed
1 month ago
1
Some Zvk tests fail with VLEN=128
#51
jerryz123
closed
2 weeks ago
2
Test sew16 (zvfh) fp tests
#50
jerryz123
closed
1 month ago
1
Zvfh Tests
#49
jerryz123
closed
1 month ago
0
Query about the test generator
#48
latifbhatti
opened
1 month ago
1
No matter what MODE is configured, RVTEST_RV64UV is generated in the assembly case
#47
Shanchuang666
closed
1 month ago
1
[GSOC] Integrated support for Zvkned, Zvknha, Zvksed and Zvksh
#46
SyedHassanUlHaq
closed
2 months ago
0
[env] remove sequencer-vector
#45
Avimitin
closed
2 months ago
1
[GSOC] integrated support for Zvbc and Zvkg instructions
#44
SyedHassanUlHaq
closed
2 months ago
1
Improve naming | update to latest spike
#43
jerryz123
closed
2 months ago
1
[GSOC] integrated support for Zvbc
#42
SyedHassanUlHaq
closed
2 months ago
6
[GSOC] integrated support for zvbb insn
#41
SyedHassanUlHaq
closed
3 months ago
21
VLEN 2048 tests size
#40
FariaaFaheem
closed
5 months ago
2
Add tests for vlseg<nf>e<eew>ff.v
#39
troibe
closed
6 months ago
2
Fix vfwmul.vv
#38
troibe
closed
7 months ago
1
for VLEN=2048 test script gives errors.
#37
akifejaz
closed
6 months ago
12
Custom tests generation
#36
akifejaz
closed
7 months ago
1
Use tail/mask undisturbed instead of agnostic
#35
troibe
closed
6 months ago
6
Zero vector registers before all tests
#34
jerryz123
closed
8 months ago
1
Test vsetvli with x0 source operand
#33
jerryz123
closed
6 months ago
0
Instructions which read at 2xSEW should be initialized with 2xSEW
#32
jerryz123
closed
6 months ago
0
Fix vfdiv.vv
#31
jerryz123
closed
8 months ago
1
Support cosim-mode tests
#30
jerryz123
closed
8 months ago
1
Bump to latest spike
#29
jerryz123
closed
8 months ago
0
Fix lmul for vsext and vzext
#28
troibe
closed
9 months ago
3
Add testdata padding for .vf4 and .vf8 instructions
#27
troibe
closed
9 months ago
2
Tests for vsext.vf4/8 and vzext.vf4/8 rely on inital values of vector registers
#26
troibe
closed
9 months ago
1
Fix test case for vmerge.vxm
#25
troibe
closed
9 months ago
1
Avoid operands which expose non-associativity of fredusum
#24
jerryz123
closed
9 months ago
1
Use https for riscv-test-env submodule instead of ssh auth
#23
troibe
closed
9 months ago
1
Remove fmax/fmin from fredusum
#22
jerryz123
closed
9 months ago
1
Add more tests which check CSR functionality
#21
troibe
opened
10 months ago
8
Check vxsat setting
#20
jerryz123
closed
9 months ago
2
Test all cases of VXRM.
#19
jerryz123
closed
10 months ago
2
Make for target 'build-patcher-spike' failed
#18
ptzheng
opened
11 months ago
10
Restrict virtual mode tests to vector load/store only?
#17
jerryz123
closed
10 months ago
2
Restrict virtual mode tests to vector load/store only?
#16
jerryz123
closed
11 months ago
1
How to use this project for plct-gem5？
#15
luojihe
closed
11 months ago
5
clean-out should only clean OUTPUT
#14
jerryz123
closed
1 year ago
1
Remove git-submodule-init make target
#13
jerryz123
closed
1 year ago
0
Need more test case for vector index load/store
#12
huxuan0307
closed
6 months ago
7
Store tests seem to check wrong address
#11
jerryz123
closed
1 year ago
7
Store tests should check memory regions touched by store.
#10
jerryz123
closed
1 year ago
1
Support v-env test generation
#9
jerryz123
closed
1 year ago
0
Support VLEN=64 tests
#8
jerryz123
closed
1 year ago
0
Set output directory by vlen/mode
#7
jerryz123
closed
1 year ago
0
Fix TEST_CASE macro to avoid out-of-bounds jumps
#6
jerryz123
closed
1 year ago
0
Switch to linking with Spike instead of patching, use upstream riscv-test-env
#5
jerryz123
closed
1 year ago
10
Add vset* and more insns
#4
FanYang98
closed
1 year ago
0
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