issues
search
enjoy-digital
/
litesata
Small footprint and configurable SATA core
Other
119
stars
33
forks
source link
issues
Newest
Newest
Most commented
Recently updated
Oldest
Least commented
Least recently updated
LiteSATA bench not initializing on SQRL Acorn CLE-215 and Alientek Davinci Pro A35T
#33
hansfbaier
opened
5 days ago
3
Improve Ultrascale(+) PHYs naming.
#32
enjoy-digital
opened
6 months ago
0
Working linux driver
#31
cyntem
closed
7 months ago
1
Add PHY support for Kintex/Zynq Ultrascale+ GTH transceiver
#30
rniwase
closed
6 months ago
2
uspsataphy.py, ussataphy.py: Fix PROGDIV to depend on data width
#29
rniwase
closed
8 months ago
1
LiteSATA Bench not initializing on Nexys Video
#28
md-raz
opened
10 months ago
0
Add/Finish ECP5 support.
#27
enjoy-digital
opened
11 months ago
3
Fix flow control during read operation
#26
rniwase
closed
1 year ago
1
frontend/dma: support multi-sector transfer
#25
gsomlo
closed
1 year ago
15
how is the serial port used?
#24
Quenii
closed
3 years ago
1
Understand why set_reset_less can't be used in streams.
#23
enjoy-digital
opened
3 years ago
0
Artix7: Allow use without 150MHz refclk.
#22
enjoy-digital
closed
3 years ago
1
Add IRQs to notify SATA connect/disconnect and end of DMAs
#21
enjoy-digital
opened
3 years ago
0
Add DMA frontend
#20
enjoy-digital
closed
3 years ago
1
Switch PHYs to LiteICLink
#19
enjoy-digital
closed
3 years ago
2
Zero delay oscillations in Vivado XSIM simulation
#18
mik1234mc
closed
3 years ago
3
Feedback / Contribution / Support
#17
enjoy-digital
opened
3 years ago
0
Add Artix7 support
#16
enjoy-digital
closed
3 years ago
2
Prepare for Artix7 support
#15
enjoy-digital
closed
5 years ago
0
CRC
#14
felixheld
closed
5 years ago
1
Fix all indentation issues in python code
#13
felixheld
closed
6 years ago
0
Adding a .gitignore
#12
mithro
closed
6 years ago
0
reported broken with LiteX > 6a7604cbb06454813541bc308791e90e051555af
#11
enjoy-digital
closed
5 years ago
1
A couple of fixes from Hasselblad.
#10
jklockars
closed
7 years ago
1
adapt simulations to new simulator
#9
enjoy-digital
closed
8 years ago
2
Wait for PLL unlock in init RX FSM when doing a full reset
#8
olofk
closed
8 years ago
1
Initialization fixes
#7
olofk
closed
8 years ago
1
For upstream
#6
olofk
closed
8 years ago
1
For upstream
#5
olofk
closed
8 years ago
1
Need to repeat last primitive after an ALIGN when sending CONT
#4
enjoy-digital
closed
8 years ago
1
Expose DRP port and power-down signals from k7 phy
#3
olofk
closed
8 years ago
1
Add .gitignore
#2
olofk
closed
8 years ago
0
Fix broken import in bist.py
#1
olofk
closed
8 years ago
3