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etf-unibl
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fpga-pwg
MIT License
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Issue #56 : Implementirati podrsku za pogresne Avalon transakcije
#58
lukavidic
closed
7 months ago
0
Verifikovati podršku za pogrešne Avalon transakcije
#57
lukavidic
closed
7 months ago
0
Implementirati podrsku za pogresne Avalon transakcije
#56
lukavidic
closed
7 months ago
0
Issue #51 : Redizajniranje testbenča brojača
#55
RadonicA
closed
8 months ago
1
Issue #48 : Uređivanje README fajla
#54
bsav98
closed
8 months ago
0
Issue #52 : Popravljanje bagova
#53
lukavidic
closed
8 months ago
0
Popravljanje bagova
#52
lukavidic
closed
8 months ago
0
Redizajniranje testbenča brojača
#51
lukavidic
closed
8 months ago
0
Issue #47 : Kreiranje dokumentacije projekta
#50
lukavidic
closed
8 months ago
0
Issue #46 : Kreiranje Quartus projekta
#49
dleg98
closed
8 months ago
0
Uređivanje README fajla
#48
lukavidic
closed
8 months ago
0
Kreiranje dokumentacije projekta
#47
lukavidic
closed
8 months ago
0
Kreiranje Quartus projekta
#46
lukavidic
closed
8 months ago
1
Issue #40 : Implementacija atomskog pristupa registrima
#45
lukavidic
closed
8 months ago
0
Issue #42 : Implementacija interrupt logike
#44
dleg98
closed
8 months ago
0
Verifikacija rada interrupt logike
#43
lukavidic
closed
8 months ago
0
Implementacija interrupt logike
#42
lukavidic
closed
8 months ago
0
Verifikacija rada atomskog pristupa registrima
#41
lukavidic
closed
8 months ago
0
Implementacija atomskog pristupa registrima
#40
lukavidic
closed
8 months ago
0
Prepare project documentation
#39
knezicm
opened
8 months ago
0
Create atomic access to time stamp registers
#38
knezicm
opened
8 months ago
0
Issue #35 : Integracija svih komponenti
#37
RadonicA
closed
8 months ago
0
Implementacija integracionog testa
#36
lukavidic
closed
8 months ago
0
Integracija svih komponenti
#35
lukavidic
closed
8 months ago
0
Issue #33 : Popravka testbencha komponente reg. fajla
#34
lukavidic
closed
8 months ago
0
Popravka testbencha komponente reg. fajla
#33
lukavidic
closed
8 months ago
0
Issue #30 : Integracija FIFO bafera i reg. fajla
#32
bsav98
closed
8 months ago
0
Implementacija testbench-a za integrisani dizajn FIFO bafera i reg. fajla
#31
RadonicA
closed
8 months ago
0
Integracija FIFO bafera i reg. fajla
#30
bsav98
closed
8 months ago
1
Issue #24 : Modifikacija postojećih testbenčeva
#29
bsav98
closed
8 months ago
0
Implementacija testbench-a za komponentu reg. fajla
#28
lukavidic
closed
8 months ago
0
Issue #26 : Implementacija komponente registarskog fajla
#27
lukavidic
closed
8 months ago
1
Implementacija komponente registarskog fajla
#26
lukavidic
closed
8 months ago
1
Issue #22 : Modifikacija FIFO bafera
#25
lukavidic
closed
8 months ago
0
Modifikacija postojećih testbenčeva
#24
RadonicA
closed
8 months ago
0
Modifikacija testbenča za FIFO bafer
#23
RadonicA
closed
8 months ago
0
Modifikacija FIFO bafera
#22
RadonicA
closed
8 months ago
2
Issue #20: Create Github action for running automate VUnit tests
#21
knezicm
closed
8 months ago
0
Create a github action for running automated VUnit tests
#20
knezicm
closed
8 months ago
0
Add support for handling Avalon bus errors
#19
knezicm
opened
8 months ago
0
Create interrupt logic
#18
knezicm
opened
8 months ago
0
Get familiar with VUnit verification framework
#17
knezicm
closed
8 months ago
0
Integrate custom logic and system time counter with FIFO and register file
#16
knezicm
opened
8 months ago
0
Create FIFO buffer for timestamps storing
#15
knezicm
closed
8 months ago
0
Create register file that can be accessed via Avalon-MM
#14
knezicm
closed
8 months ago
0
Create system time component and custom PWG logic
#13
knezicm
closed
8 months ago
0
Study Avalon-MM interface specification
#12
knezicm
closed
8 months ago
0
Issue #3: Implementacija izlazne logike
#11
dleg98
closed
8 months ago
0
Issue #8 : Implementacija FIFO bafera
#10
lukavidic
closed
8 months ago
0
Implementacija testbenča za FIFO bafer
#9
lukavidic
closed
8 months ago
0
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