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ghdl
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ghdl-yosys-plugin
VHDL synthesis (based on ghdl)
GNU General Public License v3.0
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Hierarchical signal names not escaped properly when synthesised to Verilog
#200
aquohn
opened
11 hours ago
0
Blackbox
#199
AdamKeith1
opened
2 months ago
0
Report statment and states in vhdl
#198
aniketabhiraj2004
opened
2 months ago
1
How to run unisim using cxxrtl
#197
aniketabhiraj2004
opened
3 months ago
7
Wrongly assign the name internal signal for vhdl
#196
aniketabhiraj2004
opened
4 months ago
2
libgnat-13.so module missing
#195
95lux
closed
4 months ago
2
GHDL+YOSYS formal verification, using Xilinx primitives
#194
Marceloqa
closed
2 months ago
3
Error when using plugin on M1 mac
#193
joaocolombari
opened
10 months ago
1
wire not found for $posedge
#192
GyrosGeier
opened
10 months ago
3
Skip sby tests when unavailable
#191
DanielG
closed
1 year ago
1
The project Keccak_PPL has several VHDL compilation issues (Fails to synthesize).
#190
alaindargelas
opened
1 year ago
0
The pre-built option #1 is extreamly outdated
#189
rodrigomelo9
opened
1 year ago
1
64 bits slicing problem
#188
Martoni
closed
1 year ago
2
Unable to build plugin
#187
48004800
closed
1 year ago
30
update examples build system
#186
playduck
opened
1 year ago
2
fixed VLO/VHI primitves
#185
playduck
closed
1 year ago
1
ECP5 Example fails: 'VLO' is unsupported
#184
playduck
closed
1 year ago
3
Failure to compile - ERROR: Assert `n.id != 0' failed in src/ghdl.cc:204.
#183
psi-chuffine
closed
1 year ago
2
ERROR: No such command: ghdl (type 'help' for a command overview)
#182
wklam296
closed
1 year ago
5
Linking against libgnat-9.so.1
#181
jjjt-git
closed
1 year ago
10
Assertion error on synth-vhdl_expr.adb while importing entity into yosys
#180
KelvinChung2000
closed
1 year ago
3
Error when using altera_mf lib
#179
albydnc
opened
1 year ago
4
ERROR: wire not found for $posedge
#178
ibkvictor
closed
1 year ago
3
error: clocked logic requires clocked logic on else part
#177
ibkvictor
closed
1 year ago
3
Error when using inout record
#176
albydnc
opened
1 year ago
3
Unable to build the plugin
#175
canerbulduk
opened
1 year ago
3
Error with altera vendor libraries
#174
albydnc
closed
2 years ago
4
Improper sythesis with Yosis
#173
Electro707
closed
2 years ago
0
Please note that open-tool-forge/fpga-toolchain is no longer maintained
#172
jockm
closed
11 months ago
1
Fix to block RAM handling as per https://github.com/YosysHQ/yosys/issues/3364#issuecomment-1148066807
#171
robinsonb5
closed
2 years ago
2
High impedance assignment translates to 1'x
#170
DanielG
opened
2 years ago
6
Add analysis support
#169
LAK132
opened
2 years ago
7
Error building ghdl plugin for yosys
#168
minghunghw
opened
2 years ago
14
Roadmap for a release
#167
Martoni
opened
2 years ago
1
Debian patches regarding DESTDIR and plugin install dir
#166
DanielG
closed
2 years ago
3
Use of BRAM in ICE40 ...
#165
PPlinux
opened
2 years ago
2
Another case of "wire not found for $posedge" - related to async resets?
#164
robinsonb5
opened
2 years ago
3
wire not found for $posedge
#163
kammoh
opened
2 years ago
3
Upload of ghdl-yosys-plugin to Debian?
#162
smoe
closed
1 year ago
7
make fails: unknown commands: "--libghdl-library-path" & "--libghdl-include-dir"
#161
tortik92
closed
2 years ago
40
Yosys assert: is_fully_const() && GetSize(chunks_) <= 1 failed in kernel/rtlil.cc:4532
#160
antonblanchard
closed
2 years ago
2
ERROR: Assert `n.id != 0' failed - seems related to unassigned variables
#159
JulianKemmerer
closed
2 years ago
7
raised STORAGE_ERROR : stack overflow or erroneous memory access
#158
suarezvictor
closed
3 years ago
13
Error: Info: No candidate top level module
#157
sowana
closed
3 years ago
3
Added proper components.vhdl with uppercase symbols
#156
hackfin
closed
3 years ago
6
Case sensitivity issue
#155
SiliconWizard
closed
3 years ago
8
Support for 'keep' boolean attribute
#154
anfractuosity
closed
3 years ago
1
VHDL to Verilog conversion with yosys-ghdl-plugin -- how to perserve signal names
#153
71GA
opened
3 years ago
4
Add support for Yosys $live cell (needed for liveness proofs)
#152
tmeissner
opened
3 years ago
2
ID::blackbox is not defined
#151
Rachus
closed
3 years ago
1
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