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ghdl
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ghdl-yosys-plugin
VHDL synthesis (based on ghdl)
GNU General Public License v3.0
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GHDL VHDL support
#147
PPlinux
closed
2 years ago
7
ERROR: wire not found for $posedge
#146
stevenbell
opened
3 years ago
3
RD_TRANSPARENT not set correctly for memories
#145
MJoergen
closed
3 years ago
3
Unable to synthesize large design
#144
monideepbora
closed
2 years ago
2
Makefile: use CFLAGS/LDFLAGS from environment
#143
Xiretza
closed
3 years ago
0
make fails
#142
github-4o
closed
3 years ago
3
remove yosys.diff, was upstreamed to YosysHQ/yosys
#141
eine
closed
3 years ago
0
Compilation broken
#140
zipotron
closed
3 years ago
5
Fix mult18x18d component to match yosys verilog
#139
JulianKemmerer
closed
3 years ago
1
mult18x18d component does not match yosys component
#138
JulianKemmerer
closed
3 years ago
2
GHDL synth internal state inconsistent with Yosys state
#137
rlee287
opened
3 years ago
6
Mixed synthesis with a Verilog top-level fails when parameters are specified
#136
rodrigomelo9
opened
3 years ago
2
ci: add command-line arguments
#135
rodrigomelo9
closed
3 years ago
1
Something related to deal with packages seems to break the Yosys EDIF generation for ISE
#134
rodrigomelo9
closed
3 years ago
4
Q: can I mix VHDL with Verilog?
#133
rodrigomelo9
closed
3 years ago
5
Not able to synthesize async resetable counters.
#132
trcwm
closed
3 years ago
1
Multiple use of module
#131
IIupor
opened
3 years ago
2
"ERROR: wire not found for $posedge" when synthesizing dynamic array insertion
#130
Xiretza
opened
3 years ago
12
Exiting with Found error in internal cell ($pmux)
#129
pstrueb
closed
3 years ago
0
Exiting with 'wire not found for $posedge'
#128
pstrueb
closed
3 years ago
1
ERROR: Unsupported(1): instance \165 of $midff.
#127
sambazley
closed
3 years ago
2
Testing on some designs from Opencores
#126
Chopper455
opened
4 years ago
4
Fix testsuite failing on second run
#125
Xiretza
closed
4 years ago
1
Fix rem/mod
#124
Xiretza
closed
4 years ago
1
Add reduce_xor support to the Yosys plugin
#123
rlee287
closed
4 years ago
1
[WIP] Implement a VHDL backend
#122
rlee287
opened
4 years ago
9
Failed to analyze file with synopsys package
#121
Chopper455
closed
4 years ago
1
Improve conversion of records
#120
ozbenh
opened
4 years ago
3
Unsupported(1): instance \1 of $assert.
#119
alemuller
closed
4 years ago
1
Fix $pmux port order
#118
Xiretza
closed
4 years ago
1
No longer seems to build with newest Yosys?
#117
fl4shk
closed
4 years ago
6
Generic edge causes "ill-formed clock-level" during synthesis
#116
patrickerich
closed
4 years ago
3
Incorrect "overflow check failed" raised
#115
patrickerich
closed
4 years ago
2
Thousend of 'terminate called recursively' messages and 'core' file generated
#114
rodrigomelo9
closed
2 years ago
8
Make not working
#113
alemuller
closed
4 years ago
3
Feature suggestion: add a `ghdl_write_vhdl` command to yosys through the plugin
#112
rlee287
opened
4 years ago
5
vhdl 2008 ports elaboration
#111
rodrigomelo9
closed
4 years ago
1
ERROR: wire not found for $posedge
#110
rodrigomelo9
closed
4 years ago
0
ERROR: Unsupported(1): instance \<INTEGER> of $mem_multiport.
#109
rodrigomelo9
closed
4 years ago
1
Cannot handle dynamic slicing and other operations in a single statement
#108
kammoh
closed
4 years ago
3
Build break with yosys current repo head
#107
donnie-j
closed
4 years ago
2
readme: fix docker usage
#106
eine
closed
4 years ago
1
Improve examples for Lattice iCEstick
#105
aimylios
closed
4 years ago
3
case statement 'when x to y' causes a "GHDL Bug Occured"
#104
patrickerich
closed
4 years ago
5
update README
#103
umarcor
closed
4 years ago
2
ERROR: Unsupported(1): instance \11 of $smod.
#102
rodrigomelo9
closed
4 years ago
1
ERROR: Assert `is_fully_const() && GetSize(chunks_) <= 1' failed in kernel/rtlil.cc
#101
rodrigomelo9
closed
4 years ago
3
Instancing initialized RAMs (Verilog implementation)
#100
hackfin
closed
4 years ago
7
Latches are unsupported
#99
rodrigomelo9
closed
4 years ago
6
Migration of this repo to ghdl (org)
#98
eine
closed
4 years ago
11
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