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ghdl
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ghdl-yosys-plugin
VHDL synthesis (based on ghdl)
GNU General Public License v3.0
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Instancing initialized RAMs (Verilog implementation)
#100
hackfin
closed
4 years ago
7
Latches are unsupported
#99
rodrigomelo9
closed
4 years ago
6
Migration of this repo to ghdl (org)
#98
eine
closed
4 years ago
11
Fixed URL of the ghdl/synth Docker image
#97
rodrigomelo9
closed
4 years ago
1
Support inout ports
#96
Xiretza
closed
4 years ago
0
The link to the Docker image in README.md point to no where
#95
rodrigomelo9
closed
4 years ago
11
Add min/max gates
#94
Xiretza
closed
4 years ago
1
error: clocked logic requires clocked logic on else part
#93
rroohhh
closed
4 years ago
5
GHDL crashes while trying to synthesize ZPU
#92
dkopotev
closed
4 years ago
5
Add abs gate
#91
Xiretza
closed
4 years ago
1
Fix ghdl.cc indentation
#90
Xiretza
closed
4 years ago
1
Multiplier inference optimizations
#89
hackfin
closed
4 years ago
2
Use nextpnr instead of arachne-pnr in README.md
#88
Xiretza
closed
4 years ago
3
Bad elaboration order
#87
rroohhh
closed
4 years ago
13
Recoding FSM under special condition results in non-functional synthesis result
#86
hackfin
closed
4 years ago
5
Added ECP5 example for Lattice versa devkit
#85
hackfin
closed
4 years ago
2
fatal error: 'map' file not found in yosys.h (from src/ghdl.cc)
#84
beja65536
closed
4 years ago
5
Slicing vector from array results in SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
#83
suoto
closed
4 years ago
1
Getting IIR_PREDEFINED_IEEE_1164_SCALAR_XOR then TYPES.INTERNAL_ERROR : synth-static_oper.adb:524 in specific files
#82
suoto
closed
4 years ago
2
ci: use image with pre-built GHDL
#81
eine
closed
4 years ago
3
Assignment of std_logic from generic to part of std_logic_vector unhandled.
#80
thasti
closed
4 years ago
6
Make test logs and exit codes consistent
#79
eine
opened
4 years ago
0
migrate from Travis to GHA and rework examples
#78
eine
closed
4 years ago
4
Mix with verilog?
#77
BracketMaster
closed
4 years ago
4
Assert failure in RTLIL::SigSpec::as_const() for T65
#76
Fatsie
closed
4 years ago
2
Aliased input gets wrong port name in yosys
#75
Fatsie
closed
4 years ago
0
Tighter integration with Yosys
#74
pepijndevos
opened
4 years ago
15
yosys script fails on second ghdl command
#73
Fatsie
closed
4 years ago
11
add cons_0, div, and umod
#72
pepijndevos
closed
4 years ago
2
yosys module loading error,
#71
donnie-j
closed
4 years ago
2
Compatibility for record port types (name mangling), for e.g. post synth test benchs
#70
donnie-j
opened
4 years ago
1
multi bank memories
#69
donnie-j
closed
4 years ago
4
demux inferred as memory
#68
donnie-j
closed
4 years ago
2
Add iadff
#67
pepijndevos
closed
4 years ago
1
Add Id_Smod support
#66
antonblanchard
closed
4 years ago
1
Comparing port with unassigned signal gives error
#65
Munken
closed
4 years ago
3
Add Id_Smul and Id_Umul
#64
antonblanchard
closed
4 years ago
1
Add Id_Neg support
#63
antonblanchard
closed
4 years ago
1
Fix a couple of compiler warnings
#62
antonblanchard
closed
4 years ago
1
Sign extend 32b literals
#61
pepijndevos
closed
4 years ago
8
Using Entity Instantiation
#60
se-bi
closed
4 years ago
2
Handle Id_Sextend
#59
tmeissner
closed
4 years ago
1
Function with two input arguments doesn't synthesize
#58
marph91
closed
4 years ago
2
testsuite: Add formal tests
#57
tmeissner
closed
4 years ago
3
Support for Memidx
#56
antonblanchard
closed
4 years ago
4
Handle Id_Asr
#55
tmeissner
closed
5 years ago
4
Add shift functions
#54
pepijndevos
closed
5 years ago
6
support for numeric_std operations?
#53
kammoh
closed
4 years ago
7
Using a constant from a package fails
#52
marph91
closed
4 years ago
1
Testsuite fails
#51
marph91
closed
5 years ago
3
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