hkust-zhiyao MasterRTL issues - Githubissues

hkust-zhiyao / MasterRTL

MasterRTL: A Pre-Synthesis PPA Estimation Framework for Any RTL Design

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Trained path-level model for timing feature extraction

#12 Ace-Ma opened 1 month ago
3
how can this design apply to some other RTL design?

#11 Lucas-Wye closed 3 months ago
3
Please provide the pre-train ML model or the method to train such a model

#10 Lucas-Wye closed 3 months ago
2
ModuleNotFoundError: No module named 'utils'

#9 Lucas-Wye closed 3 months ago
1
FileNotFoundError: [Errno 2] No such file or directory: '/data/user/masterRTL/ML_model/data/label/dc_label_area_pwr.json'

#8 Lucas-Wye closed 3 months ago
5
FileNotFoundError: [Errno 2] No such file or directory: '/data/user/masterRTL/ML_model/data/label/dc_label_timing.json'

#7 Lucas-Wye closed 3 months ago
1
ERROR: Command syntax error: This version of Yosys is built without Verific support.

#6 Lucas-Wye closed 4 months ago
4
ModuleNotFoundError: No module named 'utils'

#5 Lucas-Wye closed 3 months ago
3
FileNotFoundError: [Errno 2] No such file or directory: './design_hier.json'

#4 Lucas-Wye closed 4 months ago
1
Request for dataset

#3 luarss closed 5 months ago
1
File not find

#2 jyli559 closed 5 months ago
1
some issues

#1 jyli559 closed 6 months ago
3