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jakubcabal
/
spi-fpga
SPI master and SPI slave for FPGA written in VHDL
MIT License
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Maximum SCLK frequency on SPI SLAVE module
#11
federicodesario97
opened
1 year ago
2
spi slave miso test
#10
imuguruza
closed
2 years ago
1
spi slave in hw => dout_vld no creating '1' value
#9
imuguruza
closed
2 years ago
4
Question: spi slave sim with just master => slave mosi data transfer
#8
imuguruza
closed
2 years ago
4
SPI FPGA Version 1.1
#7
jakubcabal
closed
3 years ago
0
A question about sclk edge
#6
Seven-Zeng
closed
5 years ago
4
Possible Meta-Stability Issue in Slave Module
#5
daveythacher
closed
3 years ago
1
Not working on Cyclone II
#4
lucagessi
closed
5 years ago
7
Slave changes
#3
lhoyosm
closed
3 years ago
1
Support for different transfer size
#1
keesj
closed
3 years ago
2