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At least one tutorial uses `hdl/`, even for RTL source files that aren't exactly HDL but Verilog / SystemVerilog:
https://www.ece.ucdavis.edu/~bbaas/180/tutorials/file.organization.html
Perhaps …
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Hi @MarcoIeni,
I was running VUnit using this repository as a base, combined with github actions and simple but different source code.
The simulated verification fails to compile with the code …
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I tried running `make -f Makefile.himbaechel` in the `/examples/himbaechel/` directory, which produced the following error at the end. Any suggestions on this? I'm running this on MacOS with qt5 insta…
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Hello everyone!
When I am trying to build the project I get the following error:
```
1 targets failed
emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].ge…
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I am currently aiming to tape out a chip using SMIC's 180nm process. I am keeping the ibex core unchanged, but I need to embed SRAM on the chip. I use SMIC's memory compiler to generate the RAM's Veri…
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In the Makefile, I see there is the `riscv.smt_model` target, I was hoping it can generate models in SMT-LIB2 format (is that what it means to be?), but it seems that does not work for me.
The erro…
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## System information
```
MyHDL Version: 0.12: experimental work on new converter
Python Version: 3.10+
```
I am working on a new converter approach to accommodate future target languages (first …
josyb updated
1 month ago
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After we come closer to the System SBOM, we should also have HBOM in mind.
It can also cover topics like VHDL and Verilog elements.
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While creating an environment in vunit with System Verilog testbench, my simulation fails with error showing "Internal error: Cannot find 'enabled_test_cases' key".
I checked everything and looks fin…
dsp20 updated
7 months ago
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Hi
what's the roadmap of the features and any site about the throughput data?
Thanks