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Currently, we have a couple of purely structural Verilog files in OpTiMSoC: the toplevel files at various levels of the hierarchy. Creating these files is tedious and error-prone (getting wiring wrong…
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Hi I have a highliting issue on a system-verilog file while using tree-sitter on neovim.
These are my system-verilog lines of code:
![image](https://user-images.githubusercontent.com/50401154/21534…
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Hi,
I want to restrict my application to only verilog programs and not system verilog, can you help me figure out the grammar specification for only .v files?
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Hello,
No errors are shown (neither in the mode bar nor in the buffer or in the fringe) for verilog, despite errors being there. Errors are displayed for python/lisp without problems.
I have che…
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Hi,
Thank you for the great library!
I want to use multi-dimensional input and output arrays in the setup [without reshaping to 1-D].
For this, I'm using system verilog instead of verilog, …
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**Hosting details :**
- **Hosting Unit(Lab) Name** : Very Large Scale Integration Lab (VLSI)
- **Repository URL** : https://github.com/virtual-labs/vlsi-iiith
- **Branch/Tag** : master/[v1.1.3](h…
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We are at the verge of reaching 50,000 downloads in the marketplace. From this point, I feel it is good to have a structured development plan. The following are a few ideas that I have.
## 1. Suppo…
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#### Expected Behaviour
There shouldn't be a crash.
#### Current Behaviour
There is a SIGABORT failure post-routing. Seeing this failure when the arch file has a local crossbar in the DSP blo…
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While we don't know about good open-source linters for VHDL and SpinalHDL, **(System)Verilog** has got at least three: **Verilator**, **Verible**, **Slang**. Check [this](https://github.com/chili-chip…
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Would it be possible to have rust-hdl output to circt. https://circt.llvm.org/
One could then use the LLVM/MLIR to optimize the output before outputting System Verilog or VHDL.
For example rust is …