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When make the verilog, compilation process will be stuck in "[build. sc] [22/53] mill. Scalalib. ZincWorkerModule. The classpath".
[schu@yznode-big-07 rocket-chip]$ make verilog CONFIG=DefaultSmall…
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**Title: Unable to Change Read-Only Property "synth" when Building Out-of-Tree RFNoC Module with Vivado IP Cores for X410 Device**
**Issue Description:**
I am attempting to build an out-of-tree (O…
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I am sending the following sequence from Forth:
`$9a emit 36 emit $80 emit`
in a loop, and I am seeing:
```
0000000 c000 0000 0000 0000 00c0 0000 0000 c000
0000010 0000 0000 0000 00c0 0000 0000 c00…
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**Describe the bug**
A raspberry pi Zero in HID gadget mode cannot wake host computer.
**To reproduce**
Enable `dwc2` driver and reboot:
```sh
echo "dtoverlay=dwc2" | sudo tee -a /boot/confi…
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I've encountered two cases that would require configurating / generating file into subdirectories.
1. Project configuration header that would be included from other headers in the same project
S…
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Here is what error report said:
```
cd $HOME/verilator-optimization/rocket-chip && mill emulator[freechips.rocketchip.system.TestHarness,freechips.rocketchip.system.DefaultConfig].mfccompiler.compil…
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I'm simulating the single-core rocket-chip (https://github.com/OpenXiangShan/rocket-chip/tree/dev-difftest). I observe quite different simulation performance on this design with the latest version of …
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There are many similar language, but cannot be supported because of their extension of the file. For example, I am using scala(.scala), which is a Java based language, it cannot supported to generate …
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This is with a custom `maxOtherSize` (I set it to 10% instead of 5%). Maybe this is the cause?
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Using MiSTER FPGA and the ao486 core, I cannot get any MIDI sound out of multiple settings.
The Soundblaster setting output just noise, and continued to do so after I quit FastDoom. I had to reset …