leonardt fault issues - Githubissues

leonardt / fault

A Python package for testing hardware (part of the magma ecosystem)

BSD 3-Clause "New" or "Revised" License

41 stars 13 forks source link

issues

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Kratos debugging system integration

#188 Kuree closed 4 years ago
2
Hwtypes2

#187 leonardt closed 4 years ago
1
Unable to parse DPI calls

#186 Kuree opened 4 years ago
3
Add support for Vivado as a simulator

#185 sgherbst closed 4 years ago
4
Add .buildkite/pipeline.yml

#184 sgherbst closed 4 years ago
0
tests fail

#183 phanrahan closed 4 years ago
8
Add warning for no initialized clock

#182 leonardt closed 4 years ago
4
Add Icarus Verilog to Regression Testing

#181 sgherbst closed 4 years ago
0
Remove extraneous timesteps in action generation

#180 leonardt closed 4 years ago
2
Add support for poking scalar to array using broadcast semantics

#179 leonardt closed 4 years ago
0
Sv waves

#178 leonardt closed 4 years ago
0
VCS Backend Fails

#177 David-Durst closed 4 years ago
6
Using fault with magma.circuit.sequential

#176 rdaly525 opened 4 years ago
0
relax hwtypes requirement

#175 leonardt closed 5 years ago
0
Error when trying to use fault installed from pip on kiwi

#174 dillonhuff closed 5 years ago
4
Fault Failing To Find A Port

#173 David-Durst closed 5 years ago
2
Fault Fails If Top Module Name Too Long

#172 David-Durst opened 5 years ago
3
Read port value post-sim

#171 standanley closed 5 years ago
0
List Index Out Of Range Error Message Not Helpful

#170 David-Durst opened 5 years ago
2
Re-enable max_bits logic

#169 leonardt closed 5 years ago
0
Values of 33-64 don't work with verilator

#168 mbstrange2 opened 5 years ago
2
Skip CoSA tests if cosa or solver not available

#167 leonardt opened 5 years ago
0
Skip scipy tests if not installed

#166 leonardt opened 5 years ago
0
Use verilator_name for select path to verilator path

#165 leonardt closed 5 years ago
0
Compile assume/guarantee to SVA

#164 leonardt opened 5 years ago
0
Fix print internal

#163 leonardt closed 4 years ago
30
Improve handling of nested types

#162 leonardt closed 5 years ago
1
Print Doesn't Emit stdout When Running From Terminal

#161 David-Durst closed 5 years ago
2
Expect Array Of Tuples Fails

#160 David-Durst closed 5 years ago
3
Print Errors

#159 David-Durst closed 5 years ago
8
Ability To Access Ports By Variable Names

#158 David-Durst opened 5 years ago
0
Add support for printing internal signals

#157 leonardt closed 5 years ago
0
Add support for poke/expect dictionary for tuples

#156 leonardt closed 5 years ago
2
How To Print Internal Signals

#155 David-Durst opened 5 years ago
4
Support Expect With Tuple Value

#154 David-Durst closed 5 years ago
1
Document new actions

#153 leonardt opened 5 years ago
1
Add ability to write to a var

#152 leonardt opened 5 years ago
0
Real-time subprocess output; initial conditions and selective probing for Spice.

#151 sgherbst closed 5 years ago
0
SpiceTarget, user config, and increasing modularity

#150 sgherbst closed 5 years ago
0
Add osx build

#149 leonardt closed 5 years ago
0
Mixed-signal simulation, external testbenches, SRAM bits, and real numbers

#148 sgherbst closed 5 years ago
1
Minor formatting fix to correct failing pycodestyle test

#147 sgherbst closed 5 years ago
0
Features to support transistor-level verification of SRAM-like circuits

#146 sgherbst closed 5 years ago
1
Install libverilogAST and coreir on travis

#145 leonardt closed 5 years ago
0
Working with external testbenches

#144 sgherbst closed 5 years ago
2
Preliminary Verilog-AMS support

#143 sgherbst closed 5 years ago
2
Remove shell=True, fix test to skip if irun not available

#142 leonardt closed 5 years ago
3
Define variables and wait_until_(high|low|posedge|negedge)

#141 sgherbst closed 5 years ago
0
Fixes for upstream changes

#140 leonardt closed 5 years ago
0
Working with external verilog files

#139 sgherbst closed 5 years ago
4

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