orangecrab-fpga orangecrab-examples issues

orangecrab-fpga / orangecrab-examples

Example projects/code for the OrangeCrab

MIT License

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issues

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Unable to enter DFU mode using a GPIO pin

#39 tuzz closed 3 months ago
4
Add 85F support for riscv/blink and riscv/button

#38 samblenny closed 6 months ago
1
LED constraints

#37 peepo opened 8 months ago
0
Update litex references

#36 mangelajo opened 9 months ago
3
verilog: added missing pins to orangecrab_r0.2.1.pcf

#35 dh33ex closed 6 months ago
1
Added minimal PLL example

#34 ccattuto closed 11 months ago
1
Sending data to/from the FPGA with a ValentyUSB core

#33 Jelvani opened 1 year ago
0
Running python3 SoC-CircuitPython.py fails

#32 JamesTimothyMeech opened 1 year ago
2
OrangeCrab r0.2.1 no longer enumerating through dfu-util

#31 biosbob closed 1 year ago
1
amaranth: Migrate nMigen examples to Amaranth, update documentation

#30 bgianfo closed 1 year ago
1
pwm_rainbow make fails

#29 TrailBee47 closed 1 year ago
4
Building the LiteX / CircuitPython example fails with recent toolchains

#28 ccattuto opened 2 years ago
0
JSON backend fails on verilog blink

#27 shingarov closed 2 years ago
2
[Clarification] USB questions

#26 francis2tm closed 2 years ago
4
hw.r0.2: Missing pins in pin constraint file

#25 gregdavill opened 3 years ago
0
Linux on RiscV

#24 0xtrzy opened 3 years ago
1
CircuitPython isn't exporting board?

#23 tommythorn opened 3 years ago
1
device

#22 0xtrzy opened 3 years ago
0
85F compatiblity

#21 gregdavill opened 3 years ago
2
PCF files do not match the actual pinout for GPIOs

#20 jeremyherbert closed 3 years ago
4
Orange Crab r0.2 2019-12-08 won't enter bootloader mode.

#19 ghost closed 3 years ago
6
verilog: Add pwm_rainbow example

#18 nitz closed 3 years ago
1
verilog: Add blink_reset_module example

#17 nitz closed 3 years ago
1
verilog: Example cleanup

#16 nitz closed 3 years ago
1
Verilog: blink_reset: Add Windows Makefile Support

#15 nitz closed 3 years ago
1
Verilog: blink_reset: fix rst_n pin name (r0.2)

#14 nitz closed 3 years ago
5
The litex example does not work for me at HEAD

#13 la6m closed 4 years ago
11
Pinout does not show SD pins.

#12 gregdavill opened 4 years ago
0
Add full PCF for examples

#11 gregdavill opened 4 years ago
2
litex example cannot find Yosys or nextpnr-ecp5 programs

#10 opendbf closed 4 years ago
2
add LiteX toolchain setup instructions

#9 attie closed 4 years ago
5
RISC-V examples: Add SoC register map / explaination.

#8 gregdavill opened 4 years ago
0
RISC-V Blink and Button examples fail to build

#7 having11 closed 4 years ago
2
Verilog Example Build Error

#6 having11 closed 4 years ago
12
nmigen: Add an nMigen-based blink example

#5 gkelly closed 4 years ago
0
Add check for xPack GNU RISC-V Embedded GCC

#4 cdwilson closed 4 years ago
3
LiteX SoC example fails synthesis on recent Yosys

#3 shawnanastasio closed 4 years ago
4
Fix typo in help text for SDRAM command-line argument

#2 nelgau closed 4 years ago
1
Analog examples

#1 jmi2k opened 4 years ago
5