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stanford-ppl
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spatial
Spatial: "Specify Parameterized Accelerators Through Inordinately Abstract Language"
https://spatial.stanford.edu
MIT License
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Add support for `Circ`
#318
willtunnels
opened
1 year ago
0
Give more useful error when using wrong java version and trying to parse resource models
#317
mattfel1
opened
2 years ago
0
HelloSpatial cannot compile on AWS FPGA instance
#316
hecmay
closed
3 years ago
1
Add support for generic structs
#315
pyprogrammer
closed
1 year ago
0
Issue313 chiselgen vec chiselvecs
#314
mattfel1
opened
4 years ago
0
Add support for chisel codegen of Vectors
#313
pyprogrammer
opened
4 years ago
0
Moves scoping information into an explicit stack
#312
pyprogrammer
closed
4 years ago
0
Unable to compile HelloSpatial when run "bin/spatial HelloSpatial --synth --fpga=ZCU"
#311
yrq0208
closed
4 years ago
2
Add support for overridable timeouts
#310
pyprogrammer
closed
4 years ago
1
Categorical HM integration with Spatial kernel implementations
#309
mattfel1
opened
4 years ago
2
Add Multiplicative Syntax for DSE Annotations
#308
mattfel1
opened
4 years ago
0
Exception compiling HelloSpatial (isl dependency) on AWS F1
#307
feio-ai
closed
4 years ago
2
Issue305 consumers dfs
#306
pyprogrammer
closed
4 years ago
0
consumersDfs executes all-paths
#305
pyprogrammer
closed
4 years ago
0
Confirm Banking with II = 1 is correct for two accesses scheduled at different cycles
#304
mattfel1
opened
4 years ago
0
Access patterns with specific cases of || and &&
#303
mattfel1
opened
4 years ago
0
Performance bug with loadCSV1D
#302
kelayamatoz
opened
4 years ago
0
Throw Error if DRAMHost is declared inside accel
#301
mattfel1
opened
4 years ago
0
FixDiv -> SRA Bug
#300
mattfel1
closed
4 years ago
0
AXI4 Compatibilty Issue
#299
kelayamatoz
opened
4 years ago
0
Sparsity
#298
yaqiz01
closed
4 years ago
0
Switch Transformer Potential Issue
#297
mattfel1
opened
4 years ago
0
Sparsity
#296
yaqiz01
closed
4 years ago
0
Implement Dual Read Ports
#295
mattfel1
opened
4 years ago
0
Spatial Ctrl BBox + Pipe Inserter
#294
mattfel1
closed
4 years ago
1
WIP: Optimize counter bitwidth in Foreach control
#293
kumasento
opened
4 years ago
0
Disable optimized reduce for FltPt for now
#292
mattfel1
opened
4 years ago
0
Sketchy Resource Result for Memory
#291
mattfel1
opened
4 years ago
0
Pir dev
#290
yaqiz01
closed
4 years ago
0
Port FrameIn/Out to cpp backend
#289
mattfel1
opened
4 years ago
0
Optimize datapath bitwidths
#288
mattfel1
opened
4 years ago
7
Fancy Blackbox Support
#287
mattfel1
closed
4 years ago
1
Added support to read a text file and dump to the device memory directly
#286
kelayamatoz
closed
4 years ago
0
Banking experiments
#285
mattfel1
closed
4 years ago
0
IDEA cannot correctly give coding suggestion
#284
CristinaZN
closed
4 years ago
2
many erros when do bin/spatial HelloSpatial --sim
#283
CristinaZN
closed
4 years ago
4
error with compile HelloSpatial.scala
#282
CristinaZN
closed
4 years ago
3
Rewrite Rule for Modulo with Mersenne Number
#281
mattfel1
closed
4 years ago
1
Give User Some Control Over Retiming
#280
mattfel1
closed
5 years ago
2
Compilation error with Zynq fpag
#279
tissue3
opened
5 years ago
7
cl_mstr_axi_tst.sv not exists in version 1.4.7 of Amazon's EC2 FPGA Hardware and Software Development Kit
#278
tissue3
closed
4 years ago
2
Is there anyway to just generate verilog design?
#277
tissue3
opened
5 years ago
1
Random Unwanted DRAM Requests in Rogue App
#276
mattfel1
opened
5 years ago
0
Expose Stream to Frame explicitly
#275
mattfel1
closed
5 years ago
1
Broadcast + CSE = Malformed Memory
#274
mattfel1
opened
5 years ago
0
Banking Analyzer is Lying About Being Able to Bank This
#273
mattfel1
opened
5 years ago
0
MergeBuffer Banking
#272
yaqiz01
closed
5 years ago
1
Not Staging Return Value of IfThenElse
#271
mattfel1
opened
5 years ago
0
Add support for LockSRAM and Lock nodes
#270
mattfel1
opened
5 years ago
1
FIFO not duplicated during outer loop unrolling
#269
yaqiz01
closed
5 years ago
5
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