stevehoover warp-v issues

stevehoover / warp-v

WARP-V is an open-source RISC-V CPU core generator written in TL-Verilog.

https://warp-v.org

BSD 3-Clause "New" or "Revised" License

229 stars 57 forks source link

issues

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Workshop

#65 stevehoover closed 3 years ago
0
Configurator announcement prep

#64 stevehoover closed 3 years ago
57
Configurator tweaks

#63 stevehoover closed 3 years ago
0
shifting cpu_viz stage in M4_MEM_WR_STAGE

#62 vineetjain07 closed 3 years ago
0
add Code tab, make --bestsv configurable

#61 adamint closed 3 years ago
1
Resolve #58 and #59

#60 adamint closed 3 years ago
0
Configurator tweaks

#59 stevehoover closed 3 years ago
0
Configurator: Add support for SandPiper --fmt* options.

#58 stevehoover closed 3 years ago
2
Viz build fix

#57 ahadnagy closed 3 years ago
0
Add configurator

#56 adamint closed 3 years ago
0
Configurator tweaks

#55 stevehoover closed 3 years ago
0
Migrate to the new Sanspiper SaaS service

#54 ahadnagy closed 3 years ago
0
Riscv-formal basedir override PR

#53 ahadnagy closed 3 years ago
0
Ci debug

#52 stevehoover closed 3 years ago
0
Changes to reduce the size of CPUs and add sandpiper options when in …

#51 develone closed 4 years ago
0
OpenPiton Transducer in WARP-V

#50 shivampotdar opened 4 years ago
0
added b-ext and removed fpu folder

#49 vineetjain07 closed 4 years ago
0
removing head flit, propagating to |ingress_out

#48 vineetjain07 closed 4 years ago
0
Fixed speculative use of packet head/tail that should have been non-s…

#47 stevehoover closed 4 years ago
0
current state of repo does not reproduce on makerchip

#46 Ravenwater closed 4 years ago
1
Support syntax highlighting and detection of TL-Verilog by GitHub

#45 shivampotdar opened 4 years ago
4
Moved \TLV riscv_gen() into warp-v_includes submodule.

#44 stevehoover closed 4 years ago
0
Separated RISC-V definitions into separate file in warp-v includes su…

#43 stevehoover closed 4 years ago
0
update warp-v includes, cleaner hold_inst scope

#42 shivampotdar closed 4 years ago
0
ALTOPS were missing from new repo and fix for hold inst scope

#41 shivampotdar closed 4 years ago
1
changed F files include location pointing to new repo

#40 vineetjain07 closed 4 years ago
0
Fetch sv includes from new repo for immutability

#39 shivampotdar closed 4 years ago
0
Travis CI - 1 and 4 stage parallel

#38 shivampotdar closed 4 years ago
0
Resolve comments on #36

#37 shivampotdar closed 4 years ago
3
RV32IM + formal checks

#36 shivampotdar closed 4 years ago
1
Instrs

#35 stevehoover closed 4 years ago
0
Travis CI cache fix, muldiv include

#34 shivampotdar closed 4 years ago
1
adding CSR's for FP

#33 vineetjain07 closed 4 years ago
0
M Ext Second Issue

#32 shivampotdar closed 4 years ago
1
Adding F-extension in Warp-V

#31 vineetjain07 closed 4 years ago
3
Formatting of instruction decode M4 stuff.

#30 stevehoover closed 4 years ago
0
Instrs

#29 stevehoover closed 4 years ago
0
Instrs

#28 stevehoover closed 4 years ago
0
Added viz.

#27 stevehoover closed 4 years ago
0
WARP-V is now RV32IM!

#26 shivampotdar closed 4 years ago
2
warp-v added instruction encoding (F,A,D extension) and fpu reg file

#25 vineetjain07 closed 4 years ago
3
Bit width fix for instr characterization logic.

#24 stevehoover closed 4 years ago
0
Floating point

#23 vineetjain07 closed 4 years ago
0
Fixing issues with rounding mode support.

#22 stevehoover closed 4 years ago
0
Added automation to keep local version of genchecks.py in sync w/ ris…

#21 stevehoover closed 4 years ago
0
Bump riscv-formal to @03501a0

#20 ahadnagy closed 4 years ago
0
Added support for "rm" (rounding mode) field in funct3.

#19 stevehoover closed 4 years ago
0
Added proper instruction decode macros for "R2" (formerly "RI") type …

#18 stevehoover closed 4 years ago
0
Fixes reg vs. wire problem in impl Verilog file

#17 ayazulla007 closed 5 years ago
0
Csrs

#16 stevehoover closed 5 years ago
0

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