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Documentation of https://uvvm.github.io/vip_axistream.html#axistream-receive-vvc
Has a typing error in the example of axistream_receive.
 as its last argument (https://github.com/RedPitaya/RedPitaya-FPGA/blob/master/rtl/axi4_stream_cnt.sv#L17), ho…
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Allowing to leave out signals that are not strictly required can increase the flexibility of the standard. As a point of reference, I believe only the tvalid signal is actually required in the AXI4 St…
olofk updated
2 years ago
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Develop tooling to help with non-trivial flow graphs. Somewhat like the old `migen.flow` scheme.
## Features
* pipelining the components to get maximum throughput and minimum delay
* handle `st…
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The AxiStreamSink reads and converts `tdata` without respecting the `tkeep` bits. This can be a problem as some developers are driving `tdata` bits and bytes to X or U if the respective `tkeep` bits a…