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I am trying to build rust compiler from source using default method provided in the documentation for Banana Pi F3 which is RISC-V 64-bit SBC. Operating system is Bianbu 1.0.9 (it is debian based …
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Hello!
After using the synthesis tool for generating the C code for the RISC-V processor, there are make build errors while further flashing the code on the MAX78000EVKIT board using VS Code.
``…
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The [xPack RISC-V Embedded GCC](https://xpack-dev-tools.github.io/riscv-none-elf-gcc-xpack/) toolchain uses the `riscv-none-elf` triplet.
If you agree, I would like to contribute a small pull reque…
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When trying to build for esp32c3(or any riscv processor based esp32) tiny_types.c and tiny_types.h don't include the esp32/esp32_hal.inl(or .h, I don't remember).
This can be fixed by adding to the l…
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### Creating this issue to list the items which should have same format across the specification. Lets keep updating this list here as we find them.
1. Use of `application processor` instead of AP.…
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By the way,where can I get trainning about chisel develop for AXI, DMA,SRAM ,etc.
Thanks
TDppy updated
6 months ago
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If we have two ingress port signal group. Now two ways can be applied:
1.
group0 -> comparator0 -> filter0
group1 -> comparator1 -> filter1
2.
group0 & group1 -> comparator0 -> filter0
which…
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Hello team,
I have added the trigonometric instructions on riscv-gnu-toolchain. Now I am specifically looking for the steps required/process to compile my workload in Spike and Gem5 with these newly …
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Respected sir
I am working on Oracle virtual box with Ubuntu 22.04 LTS version
1. I ran the prerequisite dependency commands which gave some 404 error but was overcome using the --fix-missing
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Hi there, as I can see current riscv profile is mainly for application processor, and there is not yet a profile targeting at mcu market, maybe a mcu profile could be set, for mcu, interrupt should be…