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riscv-mini
Simple RISC-V 3-stage Pipeline in Chisel
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Branch Instruction misaligned can't trigger exception
#72
SeddonShen
opened
3 months ago
0
Store misaligned exception with the subsequent instruction's write request not flushed
#71
SeddonShen
opened
3 months ago
0
Add new
#70
daiduodedaweige
closed
3 months ago
0
I just add two files as some git test
#69
daiduodedaweige
closed
4 months ago
0
I just add two files as some git test
#68
daiduodedaweige
closed
4 months ago
0
Fix: Default make recipe not dump firrtl file.
#67
Yakkhini
closed
6 months ago
0
Problems related to asSint type conversion to verilog file (.sv)
#66
DIGI1919
opened
7 months ago
1
some problem about the code of test
#65
DIGI1919
closed
8 months ago
2
Upgrade to Chisel 6
#64
Emin017
closed
8 months ago
2
Is riscv-mini a single-cycle-processor?
#63
TDppy
opened
9 months ago
1
encountered error when performing make"firtool returned a non-zero exit code. Note that this version of Chisel (5.0.0) was published against firtool version 1.40.0."
#62
TDppy
closed
9 months ago
3
Cannot run program "z3"CreateProcess error=2, system cant find the file specified
#61
TDppy
closed
9 months ago
1
How to Generate Tile.fir or Tile.mlir in generated-src after Running `make`?
#60
Stevengre
closed
6 months ago
1
NastiArbiter IO forgot wrap in IO
#59
ProgrammerBing
opened
10 months ago
0
Upgrade to Chisel 5
#58
ekiwi
closed
1 year ago
0
Upgrade to Chisel 3.6
#57
ekiwi
closed
1 year ago
0
Strobe writes broken in TileTester.
#56
jdeters
opened
2 years ago
0
Failed all formal verification.
#55
B10615053
closed
2 years ago
2
Test hexfile creation documentation
#54
ObiWanRohan
closed
1 year ago
1
BUG in TileTester.scala #52
#53
LingZichao
closed
2 years ago
0
Is this a BUG in TileTester.scala?
#52
LingZichao
closed
2 years ago
3
Chisel improvements
#51
ObiWanRohan
closed
2 years ago
2
Unify hex files
#50
vighneshiyer
closed
2 years ago
0
Upgrade to Latest RISC-V Spec
#49
vighneshiyer
opened
2 years ago
0
switch to ChiselEnum and address some lint warnings
#48
ekiwi
closed
2 years ago
0
upgrade chisel 3.5.0 -> 3.5.1
#47
ekiwi
closed
2 years ago
0
test: add formal equivalence checks for optimized modules
#46
ekiwi
closed
2 years ago
0
format: restore decoding table alignment
#45
ekiwi
closed
2 years ago
0
replace configuration system with case classes
#44
ekiwi
closed
2 years ago
2
update libraries and merge into main project
#43
ekiwi
closed
2 years ago
0
enable scalafmt
#42
ekiwi
closed
2 years ago
0
Chisel 3.5
#41
ekiwi
closed
2 years ago
0
Synchronous read?
#40
AwaniK
closed
2 years ago
1
make run-tests errors
#39
skinterqwe
closed
2 years ago
0
Update verilator install
#38
chick
closed
3 years ago
0
Correct a instruction generating function
#37
hz0ne
closed
2 years ago
6
Is this core based on zcale ?
#36
Askartos
closed
2 years ago
0
How do I add a new register under the source code of src, and then use GTKWave to see this register when viewing the waveform?
#35
fmx1233
closed
2 years ago
1
Correct a typo in TestUtils.scala
#34
felixonmars
closed
4 years ago
0
Avoid test directory collisions
#33
ucbjrl
closed
4 years ago
1
Test directory naming simplification introduces collisions
#32
ucbjrl
closed
4 years ago
1
Add command line argument to verilator to support very wide wires
#31
ucbjrl
closed
2 years ago
0
Minimal clone of updated verilator version (4.016)
#30
ucbjrl
closed
4 years ago
0
[RFC] Upgrade to User-level ISA v2.2 and Privileged Architecture v1.10
#29
liangfu
opened
4 years ago
2
Prepare for publishing
#28
ucbjrl
closed
4 years ago
0
Basic tester treadle 2
#27
chick
closed
4 years ago
7
Underlying behavior of each module
#26
azimgivron
closed
2 years ago
0
Clean2 fixup
#25
chick
closed
4 years ago
0
Upgrade master to release 3.2-SNAPSHOT
#24
chick
closed
5 years ago
0
Proposal to Update Project to Latest Chisel
#23
chick
closed
2 years ago
4
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