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In PR #74, we design [vendor extension is guarded by vendorID](https://github.com/riscv-non-isa/riscv-c-api-doc/pull/74#issuecomment-2128844747). However, here we missed some cases like:
1. A SoC v…
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I am debugging a PCIE issue using the Icicle board.
- For one setup I connected a StarTech PEX1394B3 mini-PCIE card to the Icicle, and built a Linux image with the drivers for it.
- For another …
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Hi,
I wanted to replicate a Litex soc with a Vivado block design. I was wondering if there is any way to generate a UartLite module without anything else included since the Litex UartLite control r…
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I just got a sample of a Feed Sync disposable vape with Bluetooth and touchscreen functionality.
I have disassembled the vape and found that it is based on a JL7012F6 SoC with 16M of SPI Flash and a …
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- [ ] #22
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Hardware Model v2, https://github.com/zephyrproject-rtos/zephyr/issues/51831 introduces a new scheme for boards.
A `board.yml` is used to describe meta data of the board, for example:
```
board:
…
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Earlier this year I learned that Banana Pi and OpenWRT were teaming up to release a low cost wifi 6 router. The board is designed by OpenWRT and will be producted and marketed by Banana Pi. Here is an…
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Hello,
When I am using the reference design from the latest release [2024.06](https://github.com/polarfire-soc/polarfire-soc-discovery-kit-reference-design/releases/tag/v2024.06) and the linux imag…
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The given categories may not fit the person that a user might have met, f…
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Hi,
I'm trying to understand the trng flow and mechanism by which the SoC should handle driving the Caliptra Trng data in external as well as internal mode.
**In External TRNG mode:**
The documen…