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This issue involves extending the processor so that it can process more than one instruction per cycle. As functional units should naturally scale, the main problem is extending the frontend (to load …
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Using `MultiPriorityEncoder` from #573, one could implement a clean free RF list with superscalarity support. If I see correctly, this is already implemented in #395. (Everything is already implemente…
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how to design superscalar, out-of-order , 64-bit dual-core processor based mipsfpga,do yo have plan to do
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The compiler currently compiles `a+b+c+d` as `a+(b+(c+d))`. It should use `(a+b)+(c+d)` instead, because the latter can be executed out of order.
More broadly, we should balance trees of associativ…
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Mastercard adopts bitcoin: https://cointelegraph.com/news/mastercard-non-custodial-crypto-spending-card
DLC dev kit: https://x.com/bennyhodl/status/1831720708042260618
Statechain vulnerability d…
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**Describe the solution you'd like**
IEEE Superscalar SIMD architecture / loop parallelism or vectorization in code here can significantly speed up FP calculations, depending on the levels of floatin…
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### System information
Type | Version/Name
Ubuntu | 22.04 LTS
Distribution Name | Ubuntu
Distribution Version | 22.04
Kernel Version | 5.15.0-82-generic and 6.2.0-31-generic
Architecture…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
The instruction queue contains multiple instruction FIFOs to handle multiple parallel i…
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While working on #699 I found that increasing the size of the instruction buffer causes performance loss on a benchmark.
Here's what happened. Increased size of the instruction buffer caused higher…