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# 总结
- https://github.com/chipsalliance/Cores-SweRV
- https://github.com/chipsalliance/Cores-SweRV-EL2
- https://github.com/chipsalliance/Cores-SweRV-EH2
- 可以在fpag上跑tock[Cores-SweRVolf](https://gi…
cisen updated
2 years ago
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I want to do compliance test for Swerv EH1 Core. Can I do it using riscvOVPsim. Please guide.
Regards
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Hi all,
The rule `swerv_setup` is no longer working with the core [Cores-VeeR-EH1](https://github.com/chipsalliance/Cores-VeeR-EH1) (previous SweRV). I saw that there is a fork of this core with t…
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%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_lib.sv:403: Define or directive not defined: `RV_BTB_ADDR_HI
%Error: ../src/chipsalliance.org_cores_SweRV_EH1_1.8/design/lib/beh_li…
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Hello,
I tried to implement the SweRV Core in Zedboard fpga and ran into a routing issue when run implementation. The issue is as below:
```
[Place 30-574] Poor placement for routing between an I…
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I created the test: https://github.com/chipsalliance/UHDM-integration-tests/pull/537
It gives warnings:
```
%Warning-SELRANGE: swerv/design/ifu/ifu_iccm_mem.sv:132:62: Extracting 6084 bits from onl…
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"No paths found"
En la síntesis del 26, aparece lo mismo.
¿Wavear?
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Hi,
I synthesized SweRV-EL2 and Rocket Chip with default configuration
Rocket Chip can be synthesized up to 500MHz without timing slack.
However, SweRV-EL2 can be synthesized up to 300MHz withou…
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when i run this command:
`make -f $RV_ROOT/tools/Makefile target=default_mt`
```
only get:
VerilatorTB: Start of sim
----------------------------------------
Hello World from SweRV EH2 hart0 @…
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Greetings!!
I am currently understanding the branch prediction mechanism of SweRV El2 and I am captured by alot of confusions. It would be appreciated if I get to know about the following questions:
…