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Using the line:
`logic [PIPELINE_DELAY:1] [BANK_WIDTH-1:0] bankb_p ;`
Gives an error:
`ERROR: syntax error, unexpected '[', expecting TOK_ID or '#'`
The error can be fixed using an unpacked arr…
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Tasks;
- [x] add SystemVerilog simulator
- [x] add circuit print
- [x] add stats of the circuit (number of wires, regs, memory, ...)
- [ ] add waveform
- [x] add an example of Google Colab usag…
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I attempted to convert this project to Verilog so I could use it in Xilinx ISE.
I used a utility called sv2v (https://github.com/zachjs/sv2v).
I had to change 3 wires to reg after conversion and the…
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### Is there an existing CV-X-IF task for this?
- [X] I have searched the existing task issues
### Task Description
This repo hosts an example SystemVerilog Interface of the CV-X-IF in [src/core_v_…
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Hi there,
I've identified an issue related to the Sail-to-SystemVerilog translator. The problem arises when translating Sail code that involves the `foreach` construct.
Simply put, I suspect that …
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Currently we flatten all struct into a single bus, ex:
```
struct Operand {
a: u8,
b: u8,
c: u8,
}
fn muladd(op: Operand) -> u8 {}
```
will generate:
```
module user_module(
inpu…
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I work with SystemVerilog and UVM extensively , so I am wondering if I can somehow setup a path to the UVM installation directory so that I can get autocompletion of UVM keywords for every projects?
…
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Hi,
I am search for tree-sitter plugin for verilog/systemverilog. "tree-sitter/tree-sitter-verilog" doesn't work well for highlighting.
I am wondering how to use "tree-sitter-systemverilog" in nvi…
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Hi, I am facing the following issues while synthesizing your project in Vivado. Can you please have a look at the attached image and let me know which modules are missing?
![image](https://user-imag…
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Hello author, thank you very much for being able to open source your project, can you provide systemverilog code for FPGA implementation?