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Hello,
I am currently working with a proprietary in-house tool-chain for generating register map documentation, UVM packages, c-headers as well as synthesizable RTL that can be directly used in IPs…
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Hi, i have downloaded your openhbmc ip.
I do not now what freq and phase you should attache to clk_iserdes.
I am trying to run it at 100Mhz at the Hyperram.
Best regards
Lasse Eriksson
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**Description**
Simulation Crash on OSVVM Axi4Master. Exits with `child process exited abnormally`
**Expected behaviour**
A simulation that finishes properly.
**How to reproduce?**
I have…
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Started a discussion in the [litex-boards reporsitory](https://github.com/litex-hub/litex-boards/issues/63) about providing support for HPS in Cyclone V SoCs.
Ultimately the best way to do it is to…
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Modify the dvp_receiver module's output to be compliant with the AXI4-Stream Video Interface.
This makes it possible to use the receiver with the Xilinx [Sensor Demosaic](https://www.xilinx.com/su…
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This is an issue to track the steps needed to get FuTIL running on an FGPA. For now, we are targetting the Alveo U50 card that is in Havarti. Hopefully, the process won't be drastically different for…
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SystemRDL-compiler is missing a check, standard section 10.6.1 Semantics, point c).
"The value of the accesswidth property shall not exceed the value of the regwidth property."
In my case access wid…
jeras updated
3 years ago
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Hi, I hope you are well. I am facing the following error while regenerating the verilog files in the src_SSITH_P2 folder with `make compile` command:
```
compiling ../src_Core/Near_Mem_VM_WB_L1_L2…
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Getting this error in my small UVVM testbench. Don't understand why. Does someone have a solution?
I am using Questasim to compile the design.
`
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Hello,
I generated a netlist using Design Compiler.
I have two issues:
1. In sp_ram_wrap.sv is a module called 'sp_ram_bank' but there is no file containing this module. Where can I find it?
2. I …