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Hi!
Feature suggestion: easily deriving one `.gtkw` file to have several ones, to show the same waves for different tests. For now I have an `sh` script, but maybe similar feature could be integrat…
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I need to change a reg reset kind to SYNC in vex core. So, I try to implement by using ClockDomain object according to SpinalHDL docs.
val decodePc_Domain = ClockDomain(ClockDomain.current.r…
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How can use Verilog/system-Verilog testbench to verify the function of USB device?
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Adding this issue to track CD integration progress mentioned in SpinalHDL/SpinalCrypto#10. Will also probably touch on #793.
I will start working on it in the beginning of September.
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Hi Dolu1990,
Found a weird D-cache stuck issue. Attached the waveform. It's related to refilling. D-cache goes into line fill phase and expect loader_counter_values to go up. On the other hand, dBus_…
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#### Description
When running a simulation with a large time duration (~500k seconds), the waveform generated using the `.withFstWave` option cannot be opened in GTKWave. Attempting to load the `.f…
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The generated Verilog code contains a header like this:
```Verilog
// Generator : SpinalHDL v1.3.9 git head : 0f14fcc31e1099ab7fb106009a605d0d6e7be21a
// Date : 12/03/2020, 23:01:57
// C…
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Pcie is useful in various domain in fpga. However, there is not any facility to use pcie dma in SpinalHDL.
I'm currently working on it. Firstly, I will focus on ultrascale device, I will mainly bo…