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Hi,
I'm a Computer Science Engineering student in Spain and I'm using RIPES for my final degree's project. My aim is to add a new processor model, which is described in System Verilog.
I am follow…
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We are practicing the basic functions of Verilog. To verify the simulation results of our model, we are using three different tools, namely iverilog, vivado, and quartus, to simulate the same synthesi…
ghost updated
1 month ago
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I've ended up having this kind of design pop up several times where, essentially, I want to structure my overall project into two components:
1) A **shell** for my FPGA board, that abstracts out …
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First of all, let me say that I'm really impressed by your project! I waited for something like this for quite a while and really happy that finally we have something to work on. I even wrote [an arti…
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Hi!
I'm using clash 0.99.3.
I'm working on implementing a fifo buffer using the blockrams that can have a read port and a write port that have have different widths. The efficiency of the usage …
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Hello
I'm interested in this project, since am working on a commercial version of a FIRRTL Simulator implemented in Scala for large SoC designs. Our goal is to support Rocket and Boom simulations …
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Hi Lawrie and thanks for that great work!
As you mentioned:
> This implementation has been done from the specification, without access to any Raspberry Pi HDL. It is currently incomplete, but so…
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> Note: I'm not sure if this should be an issue or a discussion. I think you can convert between them. Feel free!
I'd like to make two small suggestions to the rule syntax. I realize this is a topi…
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### Describe the bug
The crash occured during string interpolation editing. Not sure how to replicate. Hope this log helps:
```
2024.08.21 20:11:30 ERROR Failed to tokenize input for semantic tok…
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I have taken a quick look into supporting the Synopsys VCS simulator.
It looks like similar to Cadence's `cds.lib`, VCS needs a file `.synopsys_vss.setup` for the library name-to-path mapping. http://…