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## Issue Description
`memory_libmap` pass in Yosys 0.18 and newer would synthesize LUTRAMs unsupported by nextpnr including:
- RAMS32 (manually instantiated)
- RAMD32 (manually instantiated)
- R…
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I attempted to convert this project to Verilog so I could use it in Xilinx ISE.
I used a utility called sv2v (https://github.com/zachjs/sv2v).
I had to change 3 wires to reg after conversion and the…
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I have tested the 40007 board with the correct pins file. It is very unstable and has graphical issues. The system works correctly with an original 40007. With the CPLD 40007 it always boots with grap…
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Each wave has additional description fields for texts, edges markers, etc.
Please add a "color" field, which applies a color to each wave section as "data" applies a text in the current version.
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**Describe the bug**
With #5854 being resolved I attempt to convert my [nix-fpga-tools](https://github.com/benpye/nix-fpga-tools) to a fixed output derivation again. Unfortunately when making `xili…
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Hi,
I am a newbie here. May I install NetFPGA 1G CML in a PCI Express Gen 3 X16 slot? Every PC or Server which has PCI Express Gen2 X4 or a higher one in its Motherboard, will work smoothly with…
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I am attempting to flash a bitstream to a custom FPGA board, called the [Dragon-L](https://www.knjn.com/FPGA-Dragon-L.html). It has a `Spartan-6 XC6SLX25T-CSG324` FPGA on board. I am using an Altera U…
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When I try to build for example litex_boards/targets/linsn_rv901t.py with --with-ethernet, but add ntxslots=1 to the add_ethernet line, build fails with:
> Traceback (most recent call last):
> F…
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I will be participating at the [Hack4Glarus summer edition hackathon](https://www.facebook.com/events/199003247383696/) with reicast as a project. I know some other reicast members might also join, an…
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Coming from rodrigomelo9/FOSS-for-digital-HW-design#1
> Regards https://github.com/eine/vhdl-cfg, I thought about something similar between PyFPGA and others, such as edalize, hdlmake, tsfpga, and …