-
Why does the driver read the user BAR at address 0x2000 0x3000?!
It shouldn't even try to access the user BAR at all. It breaks the whole Xilinx/AMD AXI interconnect since these addresses aren't mapp…
-
Here's the patch I've applied to litex (latest upstream version, incl. all dependencies). Also shown are the commands I'm using to (attempt to) pull data out of the SoC with `litescope_cli`:
```dif…
-
As discussed in https://github.com/llvm/circt/issues/2254 , `firtool -verilog` will append the contents of the `firrtl_black_box_resource_files.f` file into the output verilog file. This results in no…
-
axi goto 10 10
Traceback (most recent call last):
File "/usr/local/bin/axi", line 9, in
load_entry_point('axi==0.1', 'console_scripts', 'axi')()
File "/Users/jojiabraham/code/axi/axi/mai…
-
**Background:**
We are using the ESP platform for implementing a heterogeneous system. We observed that AXI crossbar implemented at the output of the Ariane core in ESP was adding 3 extra cycles of d…
-
I am able to use the fpga_pci.h and fpga_mgmt.h libraries in my code just fine when I run the code as "sudo".
When I run it as a user, I get an error...
It is a simple AXI-LITE peek/poke comman…
-
Hi All
I been have problem with my BTT borad. I follow all the instructions but I can't Z axi don't respond to screen command. It's only go down no up at all I tried deffrent things and I bought ne…
-
Hi
axi_cdc uses fifos that don't infer dual SRAM. Fifo is implemented using registers, and it is very slow.
In my design, I had to lower fifo depth to 8 words in order to be able to run at 100mhz.…
-
Hello, my application scenario requires a DDR3 controller with axi interface, so I generated my DDR3 source code based on the stlv7325 development board. However, even if DDR3 initialization is succes…
-
### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything releva…