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Hi, I'm working on the step 4: Compile the overlay project on Vivado 2022.2, ubuntu 20.04. And the kria-vitis-platforms branch is [xlnx_rel_v2022.1].
When it comes to the command `source -notrace .…
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I'm reading the KMD and UMD source code , but dosen't find the entrance or call to SystemC model. So could anyone tell me what the role the SystemC model play?
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In core-v-verif there are 8 files that use some variation of `$urandom()`. You are in the "assignees" list of this issue because git believes you authored one or more of these.
The Verissimo linte…
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Hi, I am seeking a waveform viewer that can be extended. I wondered if GTKWave supports the integration of external plugins.
The alternative idea is to fork/clone the repository and integrate the fu…
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Hello,
I am enjoying gently diving into llhd as hobby during lockdown, and in that sense, my reading of the paper and the information out there might not be as thorough as it could be, so please ig…
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The version in my computer is 5.008. When I learn systemverilog with delay, I try to simulate it. After searching the doc, I began to simulate. However, it appears that there might be an infinite loop…
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First of all, let me say that I'm really impressed by your project! I waited for something like this for quite a while and really happy that finally we have something to work on. I even wrote [an arti…
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I'm trying to use this code in a Spartan 6 board, however ISE14.7 does not support System Verilog.
Vivado supports SV but not Spartan 6 family :-(
I tried to translate this code to Verilog but packe…
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**Background**
Lockstep ("tandem") co-simulation allows early detection of divergences between behaviors of different simulation models on the same test case. Typically, an Instruction Set Simulator…
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The tests fail for the vhsnunzip_buffered.vhd top for some files. For example, a file with the uncompressed content “01010101010101010101010101010101” can be decompressed successfully with the buffere…