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Hi Tim,
this is just what I was looking for. For a while now I have been looking at logic simulators to quickly wire up some circuits and tune them before building them. There are some graphical tool…
DodoB updated
3 years ago
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## 端口连接规则
### 输入端口
模块例化时，从模块外部来讲， input 端口可以连接 wire 或 reg 型变量。这与模块声明是不同的，从模块内部来讲，input 端口必须是 wire 型变量。
### 输出端口
模块例化时，从模块外部来讲，output 端口必须连接 wire 型变量。这与模块声明是不同的，从模块内部来讲，output 端口可以是 wire 或 re…
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Good evening
Currently, add_external_library always adds its argument to the -L parameter of questa/modelsim. I guess it also always creates a statement in modelsim.ini
I just happend to stumble…
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While looking at more of the blacklisted ivtest tests I am finding that some of these indeed do not match the standard, but are allowed in Icarus because this functionality is support by commercial si…
caryr updated
3 years ago
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> **Describe the bug**
It looks like if I set up a task with the following in the config/task.conf:
```
[SCRIPT_PARAM_MIN_ROUTE_CHAN_WIDTH]
end_flow_with_test=
vpr_fpga_verilog_formal_verifica…
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Hello :wave: Cool project!
I just wanted to ask what is planned for the Verilog generation in the TODO section of the README? I'm a Verilog RTL developer and would be keen to contribute to this pro…
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I want to do compliance test for Swerv EH1 Core. Can I do it using riscvOVPsim. Please guide.
Regards
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https://github.com/David-Durst/aetherling/blob/4cc822aa06eae30a01f539524b2b585d6f73f9bc/tests/haskell/test_downsampleStencil.py#L37
The above line of the test takes 3-5 minutes. However, the python…
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According to at least two users from #449 (who both seem to be using Questa), cocotb can be used in back-annotated sims. We should advertise that point and have at least a basic how-to on it.
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Hi , I am generating verilog file through gen.py and I did see a top level verilog file in the "build" folder. However , I found I missed all the submodules used in the top level, like "BUFG"or "IOBUF…