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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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Xilinx transitioned from xilinx SDK to vitis in vivado 2019.2.
In this transition, they obsoleted their "hardware description file" (.hdf) format and replaced it with a new file format (.xsa).
U…
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XDC is the new file format used for constraints in Vivado. To be able to parse designs which use XDC file format we need a parser for it.
The XDC file format is described here -> https://www.xilinx…
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I have been trying to carry out IP generation for vision-related examples, while I have been able to carry out synthesis there is an issue that I am facing during co-simuation.
I am using Vitis HLS…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- […
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When running axidma_transfer (or the benchmark example) on PetaLinux 2017.2, I am getting "axidma: axidma_dma.c: axidma_start_transfer: 305: DMA receive transaction timed out".
My Vivado 2017.2 desi…
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there are some warning below.
1. WARNING: [VPL 17-301] Failed to get a license for 'ap_opencl'. Explanation: The license feature ap_opencl could not be found.
2. WARNING: [VPL 60-1142] Unabled to re…
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Add the ability to separate out generated code by namespaces. So spirit:version creates a Version class in a Spirit namespace and xilinx:version creates a different Version class in the Xilinx namespa…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Ok so basically, I need to use CVA6 to add a peripheral to it. For that I want to open …
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Hi! I meet some problems.
**WARNING: [HLS 200-885] Unable to schedule 'load' operation ('__Val2__') on array 'buffer_data_V' due to limited memory ports. Please consider using a memory core with mo…