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Hi authors,
Just wonder why U250 is not supported, given U200 and U280 are supported? are there any technical challenges when handling U250? If I want to port it to U250, would that be hard?
B…
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Hello,
We are trying to build the project for U280.Our command is:
make ips
make create_prj_alveou280-fns-single-toe-iperf
make implement_alveou280-fns-single-toe-iperf
We found that Vivado 2018.…
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![image](https://user-images.githubusercontent.com/26862588/96945348-1c191d00-1510-11eb-8a0d-929290145c6b.png)
Exception in thread Thread-4:
Traceback (most recent call last):
File "/usr/lib/…
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Hi I have been trying to run hello world on the Xilinx alveo boards but I am constantly getting this error
utils.mk:30: *** XILINX_VITIS variable is not set, please set correctly and rerun. Sto…
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In the Alveo U280 the pin D32 must be set to 0 from the design https://www.xilinx.com/support/answers/72926.html. Otherwise, the board can brick
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Hi,
I see you have mentioned that Limago supports Alveo U200, so how about Alveo U280 ?
Are there any differences for Limago from U200 to U280 ?
Thanks a lot.
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Hi,
I was trying to run the PLRAM example in the repo, and ran into some issues when compiling it with v++. When I compile the source directly, as https://github.com/Xilinx/Vitis_Accel_Examples/blo…
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Hi,
I noticed that in the submodule/cmac directory, it created two CMAC IPs, for example,
```
alveou200_board = cmac_ALVEOu200_0 cmac_ALVEOu200_1
```
However, it seems only one has been in…
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Building the hbm_bandwidth example, either as is, with 8 CU, or with only 2 CU, seems to fail to meet timing on the Alveo U280 accelerator card using SDAccel 2019.1. The log file is provided below. Pe…