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I have generated file occamy_mesh_floo_noc.sv successfully and I want to make a Simulation in Vivado. File floo_narrow_wide_chimney.sv is a submodular of occamy_mesh_floo_noc.sv and it includes regist…
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Hi Taichi,
Thanks for taking care of this project! I am trying to compile it with Vivado, but I have some problems with Xelab, so I need some help.
More specifically, I tried these versions and …
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I seem to have no problem using iio-emu with IIO Oscope but I'm having problems with gnuradio. Typically I use gnuradio with real hardware, as well as iio_demo from the no-os library. Both of those …
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Hello @JeanRochCoulon, @zarubaf
I know that this Pull Request is now merged and closed, but I think we have an issue here: we are keeping a redundancy in the definitions for the AXI interface.
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I have your design running in nexys A7 with an EL2 core.
When I do a sequence of writes to an I/O port, such as GPIO, and my code is running in ICCM, the writes are lost, except for the last one. …
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The CVA6 can communicate with any component throw AXI interface, or he can just access to memory location?
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In [hwh_frontend.py](../blob/main/pynqmetadata/frontends/hwh_frontend.py)(line 485ff) there is a check, tries to map the "INTERFACE" to a portname.
If there is a AXI_Full port, the `INTERFACE` prope…
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The Bus Master VCI documentation suggests that `write_bus` or `burst_write_bus` is blocking. I'm trying to understand what is meant by "blocking" and how this is enforced. These questions stem from m…
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For this version, would it be possible to change the bus width size of mem_nasti interface with the memory controller from 64 to 128 bits?
For instance, changing 64 to 128 below:
```
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
On page A3-45 (AXI3 write transaction dependencies), the [AXI spec](https://developer.a…