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I've been thinking long about having some multiplatform (windows and gnu/linux), free (libre), lightweight and standalone tool to analize large bodies of VHDL 2008 code at block/RTL level. That tool w…
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More of a feature request for a frustrating modification, than an issue
I'm trying to add a toAxi4() method to DBusSimpleBus (because AXI Shared isn't part of the AXI spec), so I've created a subcl…
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HI Designer,
I could see below line of commented text just above adv_dbg_if instantiation in "core_region.sv" module.
// TODO: remove the debug connections to the core
Q1. What does it …
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calculate beats returns an 8 bit vector.
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Hi all,
I would like to have a Slave AXI4 port on the rocket in order to access the SystemBus from an AXI4 master device. So I include the trait HasSlaveAXI4Port and HasSlaveAXI4PortBundle in the T…
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While I realize it's not a full priority, this tool could be very powerful overall- with a comparable thing for each vendor's or Open Source project's macroblock assembly tool.
Not all potential pr…
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the blob/ directory doesn't exist in the repo anymore... And it doesn't look like CoreQSysAvalon.scala file made it across or was stripped from the master branch. How does one set their HDL definiti…
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Hello,
When I make fpga-images-zedboard/boot.bin for zed I get the following error.
Does anyone know where this is coming from ?
PS: I've checked my licence and it's working.
Thank you…
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Verilog has useful feature some people are used to using. It's an assignment signals concatenation to another signal.
In Verilog it look's like: `assign {a,b,c} = z; `
Chisel3 has a `Cat()` fun…
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Howdy,
I'm trying to build the memcpy example for the KU3 with Vivado 2016.4, and am running into errors during the synthesis of 'psl_fpga'. Below is the results of my `make` attempt
```
$ make…