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RSD looks like it would be a super interesting addition CPU core option for the [LiteX Ecosystem](https://github.com/timvideos/litex-buildenv/wiki). LiteX already supports multiple different RISC-V co…
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Hi all,
I'm completely getting lost through the tutorials and "full documentation". I really did not know where to request for help except here. (so I'm very sorry if this issue is not like a real is…
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i have trouble using the hardware JTAG interface over the Raspberry Pi Debug HAT after the system is fully booted: the JTAG programmer reports
> TDO seems to be stuck at 1
i think the GPIO/retro…
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Have you tested Lizard on an FPGA at all? What type of resource usage do you think it would use? (How big is the number of gates in the ASIC flow?)
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I generated a litex SoC and deployed it to a Digilent Arty using this command:
```
python3 -m litex_boards.targets.digilent_arty --bios-format float --cpu-type femtorv --cpu-variant gracilis --vari…
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Support PCIe “[Non-Transparent Bridge](https://events.static.linuxfound.org/sites/events/files/slides/Linux%20NTB_0.pdf)" (NTB) function could be a great interest for Corundun as a DPU enabler?
One…
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Hello, I've been studying what you've posted and I'm a student just starting to learn about the FPGA. When I follow the steps in the README, I encountered a problem with the I/O in the picture, if you…
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
Red Semi is trying to get Linux running on the Nexys Video build of the CVA soc, and th…
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**Describe what aspect of our project needs to be researched**
Look into how we can boot Linux on our DE1s with SD cards.
**Additional context**
Perhaps if you manage to get it working, add some …
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Hi,
do you have an example/tutorial to use DMA on Zynq with u-dma-buf ?
I already have a Vivado design with a PL FIFO filled by a counter for Microzed (Zynq-7000) that work
with dma-proxy (Xilin…