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Using OSS CAD Suite, with:
```
Yosys 0.24+1 (git sha1 7ad7b550c, x86_64-apple-darwin20.2-clang 10.0.0-4ubuntu1 -fPIC -Os)
Apycula 0.5.2.dev3+g16a91ef
GHDL 3.0.0-dev (2.0.0.r515.g78016…
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yosys \\
-p \\
"ghdl --std=08 --workdir=build -Pbuild --no-formal neorv32_iCESugarv15_BoardTop_MinimalBoot; \\
synth_ice40 \\
-top neorv32_iCESugarv15_BoardTop_MinimalBoot -dsp \\
-js…
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**Description**
When running our standard test iCE40 flow for J-Core J1, GHDL now reports an internal error.
**Expected behaviour**
GHDL should create a netlist with --synth or though the yosys p…
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### Version
Yosys 0.24+10 (git sha1 3ebc50dee, clang 11.0.1-2 -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
compile yosys without GHDL support (set this in Ma…
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**Description**
PSL "p[+]" doesn't catch an assert it is supposed to catch.
This is a continuation to: https://github.com/ghdl/ghdl/issues/2373
**Expected behaviour**
catch the assert at cycle…
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I can't use the plugin, it appears error ERROR: No such command: ghdl (type 'help' for a command overview) after following the installing instruction.
How can I solve the problem?
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Hello everybody, first, thanks for this amazing work!
Well, I have at home the board AlhambraII (iCE40) and the ULX3S (ECP5), I am using Yosys with the GHDL plugin. I wanted to synthesize using Yosys…
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I tried to generate Verilog output on a fresh ubuntu machine and ran into some problems. This is to document the problems and solutions. This information should probably be added to the wiki page some…
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```
library IEEE;
use IEEE.std_logic_1164.all;
entity counter is
generic( -- reusable constants in the counter logic
Clock_freq : Integer := 50_000 ; -- high clock frequency in …