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The tests fail for the vhsnunzip_buffered.vhd top for some files. For example, a file with the uncompressed content “01010101010101010101010101010101” can be decompressed successfully with the buffere…
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I'm wondering if there is any ability to call a SystemVerilog/UVM Task/Function from Cocotb.
Instead of living in purely Cocotb, or purely UVM, is it possible from the python side to direct and con…
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This guide lists SV interfaces as [problematic](https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md#problematic-language-features-and-constructs) and that their use is discourage…
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The goal is to both:
* Make it easier for all people discovering SpinalHDL (knowing VHDL and Verilog might help but it is not a requirement)
* Make it easier for people to find information
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I want cocotb output to go to my console, not the VCS window
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First thank you so much for doing this.
I think the world really needs a Forth processor written in System Verilog. I believe the J1 is done in Verilog, the EP32/24/16 are in VHDL, and the MicroC…
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Hi
I attempted to compile Pulpissimo on ZCU104. It ends up with timing constraints aren't met:
Current Timing Summary | WNS=-7.567 | TNS=-29782.275
The procedure I followed is:
1. download pulpis…
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@LarsAsplund, @kraiger and @umarcor,
I would like to propose a broad strategy for co-simulation with VUnit. I really like what @umarcor has been working on, but I think his approach leaves most o…
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### Before start
- [X] I have read the [XiangShan Documents](https://xiangshan-doc.readthedocs.io/zh_CN/latest). 我已经阅读过香山文档。
- [X] I have searched the previous issues and did not find anything rel…
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Hello!
SystemVerilog added the system tasks `$fatal`, `$error`, `$warning`, and `$info` (20.10). However, sv2v does not convert them at all, causing Verilog tools to fail. It would be nice to conve…