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This is a proposal: let us make ChiselVerify a more generic testing tool also for Verilog and VHDL designs. Something like, but better than, cocotb.
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#### Expected Behaviour
We should have no compiler warnings
#### Current Behaviour
Fasm has a few warnings
/home/runner/work/vtr-verilog-to-routing/vtr-verilog-to-routing/utils/fasm/test/test_…
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Hello :wave: Cool project!
I just wanted to ask what is planned for the Verilog generation in the TODO section of the README? I'm a Verilog RTL developer and would be keen to contribute to this pro…
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### Version
Yosys 0.37+1 (git sha1 e1f4c5c9cbb, clang -fPIC -Os)
### On which OS did this happen?
Linux
### Reproduction Steps
hlblk167_reg
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Hi,
Here is my proposal for Verilog mapper.
I made this dedicated mapper to be very simillar to a generic mapper, meaning:
. Pattern
. Clear
. Prefix
. Icon
It supports:
. Multi-line pat…
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Hi,
I'm looking to improve the verilog / systemverilog analyzer. What I don't like about the current behavior is that for whatever reason the definition search generally comes out empty. E.g. when …
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Are there any plans for dumping verilog testbench? It is always needed for post-simulation.
I think the `VerilogTbDump` implementation in https://github.com/ucb-bar/dsptools/blob/master/src/main/sc…
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Hi,
I added Verilog language. How can I get a push access right?
Thank you,
Goran
baltazarstudios.com
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Can we get an an implementation of this mapper in Verilog so that it'll run on a PowerPak? I'm aware that the PowerPak has only 544 KiB of RAM, but perhaps it could be made to work by using half of th…
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