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https://github.com/Xilinx/Vitis-Tutorials/tree/2022.2/Vitis_Platform_Creation/Design_Tutorials)/[01-Edge-KV260]/step2.md
xsct
createdts -hw ../kv260_hardware_platform/kv260_hardware_platform.xsa -…
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I'm planning to use your DMAs in a high performance design. Since DDR delivers data after several clocks, it would be ideal if the DMA can issue multiple outstanding AXI transactions, without waiting …
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Hi it seems the changes needed for 2021-2023 is minor.
```
diff --git a/examples/alpha250/adc-dac-dma/block_design.tcl b/examples/alpha250/adc-dac-dma/block_design.tcl
index e28f2090..edb64099 10…
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In the past I succeeded to simulate the platform using the SDK and Xcelium. However when I checkout the most recent version of Pulpissimo, building using `make build-incisive` fails with the following…
bbo49 updated
3 years ago
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### Is there an existing CVA6 bug for this?
- [X] I have searched the existing bug issues
### Bug Description
When using cva6.py with `--axi_active="no"` and vcs-uvm tesbench simulation will fail o…
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Is it possible to await a specified command index with AXI VVC? I'm trying to do:
```vhdl
axi_read(....);
cmd_idx := get_last_received_cmd_idx(AXI_VVCT, AXI_VVC_IDX);
await_completion(AXI_VVCT, AX…
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Seems commit 83d3bded6312449766385730ab07b3afde1adbfe from years ago completely breaks RX on the AD9361. Prior commits of this file works perfectly for us, but the changes in this commit breaks it. Wh…
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https://github.com/jameshegarty/rigel/blob/master/platform/axi/dramreader.v
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I'm working to get Pulpino to compile in Cadence Xcellium. I've hit an issue where there is a missing definition for module XBAR_TCDM_FC / L2_MB_INTERCO
code snippet:
XBAR_TCDM_FC
#(...)
L2…
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In [hwh_frontend.py](../blob/main/pynqmetadata/frontends/hwh_frontend.py)(line 485ff) there is a check, tries to map the "INTERFACE" to a portname.
If there is a AXI_Full port, the `INTERFACE` prope…