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Instruction `0x5036` is illegal (c.lwsp with rd=0) according to riscv specification but whisper is not decoding it as illegal.
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Hello, Our group used the FPGA-based SweRV EH2 core in a project, and wanted to use FreeRTOS SMP on it to make full use of the cores.
But the freertos and rtosal in WD-FW do not seem to support …
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At CoreMark Test ,
I achieved 3.62 ,lower than the official website‘s value of 4.3
How to configure to reach 4.3 in the CoreMark test
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I'm using the Vivado Tcl hook scripts in my flow (taken from the OpenTitan examples) but I've been trying to write some common Tcl procedures that I would like to call from those hook scripts. For ex…
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Vivado 2019.1 can't compile, but actually the code in `swerv_wrapper.sv` looks like correct SystemVerilog to me.
`fusesoc/workspace/build/swervolf_0/nexys_a7-vivado/swervolf_0.runs/synth_1/runme.lo…
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Hi, I achieved 5.0 at CoreMark test by running EH1 in FPGA, using master branch and the configurations you gave in the doc "SweRV_CoreMark_Benchmarking.pdf". But in your web page "https://www.westernd…
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En el archivo swerv_wrapper.sdc las líneas 9 y 10 (comando set_units) no está soportado
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How would I use riscof to validate the SweRV RH2 core from Western Digital?
https://github.com/chipsalliance/Cores-SweRV-EH2
I expect that I have to use an EDA tool, like Cadence Xcelium, but I ha…
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**Note: I posted this issue in chipalliance/Cores-Swervolf repo as well. Posting here, because its quite active repo. Hope everyone will understand.**
I am trying to do compliance test for swerv co…
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I am trying to do compliance test for swerv core using the mentioned guideline, but my result is;
![0th Pic](https://user-images.githubusercontent.com/58413763/134629083-379e2355-9043-4f95-8275-1f2…