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`yosys> plugin -i systemverilog
ERROR: Can't load module `./systemverilog': /usr/bin/../share/yosys/plugins/systemverilog.so: undefined symbol: _ZN5Yosys4Pass11on_registerEv`
ubuntu 20.04 LTS in W…
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Populate UHDM with all the SystemVerilog constraints objects from the Surelog AST and internal (new) datastructures.
Related to issue: https://github.com/alainmarcel/UHDM/issues/185
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# Add a Verilog / SystemVerilog support to [Sphinx](https://sphinx-doc.org)
# Brief explanation
We use [Sphinx](sphinx-doc.org) for documentation heavily. Sphinx currently doesn't support Verilo…
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It seems that the iverilog invocation doesn't allow for SystemVerilog support:
https://github.com/google/xls/blob/c330e64365e56439ab9496159aa8664c6cd5eb6a/xls/simulation/simulators/iverilog_simulator…
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A record type is a tuple with named fields. I'm guessing it will be possible to mostly just treat records as special tuples. Tupleindex instruction would work the same. Might need a new instruction kR…
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I can't seem to pass an array to a _SystemVerilog_ function.
The following code (`tmpdbg.sv`):
```systemverilog
01 module foo;
02 logic [7:0] y[0:3], i;
03
04 function logic [7:0]…
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Hello,
I have this in `Languages.txt` for adding a custom language SystemVerilog:
```
Language: SystemVerilog
Extensions: v vh sv svh
Line Comment: //
Block Comment: /* */
M…
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### Checking the checkers
https://github.com/amiq-consulting/svaunit/blob/master/docs/SystemVerilog_Assertions_Verification_with_SVAUnit_paper.doc
https://www.amiq.com/consulting/wp-content/themes/A…
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I noticed that the VUnit testcases in a SystemVerilog testbench will always fail if their testcase name contains a colon. I attached a minimal example including a simple run.py script and a minimal te…
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While “legacy” integration is easily dismissed as a “detail”, in practice it is anything but. Getting this right gives designers an easy on-boarding path to a particular technology. Getting it wro…