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Bugs I noticed when I looked at promotion trees using Howard's Promotion Tree UI mod.
Logistics requires range promotion for ranged units. There is no blitz in shock branch. Logistics should not be av…
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After just cloning the code and running `py.test` in the top level directory, I see this error
```
Hwacha/test_broadcast.py:1: in
import broadcast
Hwacha/broadcast.py:1: in
import tweepy
E …
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This is too vague of a report right now but I'm pasting this here so I don't lose it or forget about it:
Will update later today.
```
/scratch/colins/rocket-chip/firrtl/utils/bin/firrtl -i /scratch/c…
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Well, it's actually O(m^n), where m is the level of when nesting.
The following short module, which has a 5-nested when statement repeated a few times, results in about 550 KB of code. If you replic…
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After the Chisel compiler output'ed the following error message, it went ahead and generated incorrect Verilog:
[error]: All IO's must be ports (dir set): /_io_debug_vlen_7 in class hwacha.Sequencer_…
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When instantiating multiple instances of a module in a design the generated Verilog may contain multiple, redundant module definitions which are each instantiated once. For example, pulling the curre…
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It looks like there's a mismatch between riscv-isa-sim and riscv-opcodes with respect to the hwacha instructions.
When I make riscv-opcodes in order to update riscv-isa-sim/opcodes_hwacha_ut.h, there…
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Following the instructions on http://riscv.org/download.html#tab_isa-sim to simulate a new instruction, I always run into a build error:
make: **\* No rule to make target `insns_ut/ut_beq.h', needed …
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Just heard about [hwacha](https://github.com/sdball/hwacha), which could improve times due to its ability to run checks in parallel. Thoughts on using it?
parkr updated
10 years ago