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The installer needs to be able to chown files in the working directory. This is not possible with a bind mount from the host. Copying files into the container in the first step of docker.sh avoids t…
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Hello, I am investigating in using ibex for my University research project and I have some problems trying to get the example (targeting Artix A7-100T) to build correctly. I took a look in the example…
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I'm trying to load a .elf file onto an Ibex riscv core on a CW305 FPGA using the following shell script [provided by the Ibex developers](https://github.com/lowRISC/ibex-demo-system/blob/main/util/loa…
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Hello! Thank you for working on and releasing Manta, very excited to use it more and see where it goes!
This evening I was trying to use the logic analyzer core for the first time, but I'm running …
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Hello !!
I am trying to flash my spartan-6 FPGA without ISE, finally I got this repo. And it works great for programming.
But not able to flash my bit file. Its prompting "Wait: error timeout: ff…
Dv-p updated
7 months ago
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I am working on a Nexys Video board, i've tried multiple boards that kept facing issues, however I got my hands on this board and I am trying to run a simple template on it to check that everything wo…
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Hi charles,
How will it be possible to run linux on Litex-Naxriscv like as https://github.com/litex-hub/linux-on-litex-vexriscv
I like to run (NaxRISCV 64 bit ) RISCV 64 Debian Linux on FPGA…
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I am wondering how can i integrate these both part of code which are in different location
NaxRiscv/src/main/scala/naxriscv/platform/tilelinkdemo/SocSim.scala
https://github.com/SpinalHDL/NaxRis…
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I was following the instructions in issue: https://github.com/microsoft/cheriot-safe/issues/3
Neither the hello world nor the charity sanity check are producing any UART output for me while using t…
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Hey there!
Can we port ztachip to the following FPGAs with less than 100,000 LUTs:
1. Digilent Cmod A7-35T: Artix-7 with 35,000 LUTs
2. Cmod A7-15T: Artix-7 FPGA Module with 15,000 LUTs
3. CrossLi…