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Dear Maintainers,
Thanks for providing svlint (and sv-parser). The following piece of example code should be valid systemverilog from my understanding (ignore that the functionality does not make sen…
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Hello,
I got this error when simulating ESP. Can anyone help?
> ** Error: /mnt/Archive/Downloads/esp/rtl/src/techmap/unisim/tap_unisim.vhd(30): (vcom-1598) Library "unisim" not found.
** Error: /…
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I am trying to move ara on VCS, but met too many errors, and they are hard to fix.
Do you have the correct Compilation Options on VCS or irun? Or a script of running by VCS?
These are examples of…
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This ticket is a follow up issue to https://github.com/pulp-platform/pulpissimo/issues/104. I still have the same issue on a fresh master version of pulpissimo with a recent sdk (followed documentatio…
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Coming from rodrigomelo9/FOSS-for-digital-HW-design#1
> Regards https://github.com/eine/vhdl-cfg, I thought about something similar between PyFPGA and others, such as edalize, hdlmake, tsfpga, and …
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I am having trouble getting the vector trace generator to work.I tried to compile with the given command but nothing.I tried
make bin/${rv64uv-ara-vxor}.ideal for example but all is returning is : N…
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Hello, when I try to change Ara hardware configuration to 16_lanes error alert like below
my command is
cd hardware
make clean
make verilate config=16_lanes
Error is like below.
What is th…
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![Error during make](https://github.com/openhwgroup/cvw/assets/142871238/38f0237e-3527-40f3-9bb3-4a707af03fe3)
I am simulating the core CVW .After following the steps outlined in the Git reposito…
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### Description
https://opentitan.org/book/hw/top_earlgrey/index.html says to execute this command, and it executes successfully.
NOTE: the HTML does not say which directory to run in, it would be u…
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[hdl.zip](https://github.com/nickg/nvc/files/15228964/hdl.zip)
The attached example file top.vhd instantiates work.ram with a generic set to the value INIT_LINE("default.txt"), which is not a glo…