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Hello sir,I fineshed the simulation of booting Linux for a while,and I want to learn more about this project,that's why I want to load it on Xilinx FPGAs to verify this project ,I'd like to how many f…
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### Background Work
- [X] Yes, I searched the [mailing list](https://groups.google.com/forum/#!forum/chipyard)
- [X] Yes, I searched [prior issues](https://github.com/ucb-bar/chipyard/issues)
- [X] Y…
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**Describe the bug**
With the removal of labels, DT devices get its `name` set to `DT_NODE_FULL_NAME(node_id)`. The problem is that such name is not necessarily unique, e.g. this is valid in DT:
…
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### Operating System
Ubuntu 22.04
### Other Linux
_No response_
### Workflow Version
v0.3.32
### Workflow Execution
Command line
### EPI2ME Version
_No response_
### CLI command run
`NXF_VE…
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Hi everyone,
I have a dubs about the regeneration process of the Verilog of the VexRiscV core, in particular I trying to modify the core inside the pythondata-cpu-vexriscv_smp repository and adding…
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I am student from Texas A&M university as my professor wanted to research on RISCV with multizone. To continue we started with the official website https://github.com/hex-five/multizone-sdk on our vir…
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# Sign-Off
https://github.com/tock/tock/issues/3116#issuecomment-1230330230
# Motivation
At the end of July 2022 we discussed doing a release before incorporating the AppID changes. This woul…
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**Describe the bug**
cannot upload neorv32_exe.bin for demo CFS with nexys-a7-test-setup. The upload process freezes
**To Reproduce**
Switch IO_CFS_EN=true in neorv32_top.vhd then restart synthes…
JC-LL updated
9 months ago
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Hello, i am trying to program a zedboard using openocd to a ibex core. The output error is this one:
```
./util/load_demo_system2.sh halt ./sw/c/build/demo/hello_world/demo
Open On-Chip Debugger 0.…