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I'm maintaining out-of-tree riscv-compliance target code for two RISC-V implementations (SERV and SweRV). I had some bug reports coming in recently that made me realize that the current master had an …
olofk updated
3 years ago
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SweRV still uses a custom generator script and it seems that it's file list is outdated (#894)
It should be fairly easy to migrate it to use [FuseSoC generator](https://github.com/SymbiFlow/sv-tests/…
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when I run my code with %m format, verilator adds one more layer of hierarchy to the output vs VCS/XRUN .
Is this intentional?
verilator gives something like TOP.tb vs just tb for
$display("%m")…
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riscv64-unknown-elf-gcc -Isnapshots/default -g -O3 -funroll-all-loops -mabi=ilp32 -march=rv32imc -nostdlib -c /builds/gitlab/gliwice/Cores-SweRV/testbench/tests/cmark_dccm/cmark_dccm.c -o cmark_dccm…
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Hi All,
This is Aravinda from CircuitSutra Technologies, India.
Need help in understanding the 'interrupt' feature of the SweRV-ISS. Can some one please point me to an example or a suitable doc…
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I'm trying to compile run a swervolf simulation from a clean installation, using `Verilator 4.033 devel rev v4.032-73-gdef40fa`.
Shortly after kicking things off, I get greeted with the following e…
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Hello,
SweRV RISC-V files do have problems mentioned in topic.
The code is working actually, but correct compile order has to be specified.
Namely preprocessor can be called only for a specific f…
Nic30 updated
3 years ago
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I'm working on bringing lvgl v8.1.0 support to Zephyr (which currently uses v7). During the review of my PRs it was suggested that we should switch to using LVGL's own Kconfig to allow for easier upgr…
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I have a Zedboard fpga and want to integrate this Core into it. Can I do that with this repository? What are the detailed step-by-step on how to do it? I would be really appreciate if someone could he…
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