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Hi, I have met one problem when I install 3proxy through RPM(0.9.3),the default conf file located at "**/usr/local/3proxy/conf/3proxy.cfg**", some folder are missing,for example:
>log /logs/3proxy-%y…
xzycn updated
2 years ago
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I'm trying to create and load snapshots for the Qemu side in a cosim enviornment using the qemu monitor. With a separate qemu instance for the zynqmp PMU I can't seem to load a saved VM regardless of …
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I'm on the current `sycl/unified/next` branch and using Vitis 2020.2 with a `xilinx_u200_xdma_201830_2` target. Compiling the `single_task_vector_add` test case works fine but it fails once `vpl` is c…
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Hello, after following the build tree instructions for the Nv_small configuration I try to continue with the testbench build, but it doesn't work. Do you have an idea of the cause ?
yago@Linux-2:~…
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When I am trying to build the cloned repo. After all the compilations and exports its failing at specially building for spdlog. I am currently using an ubuntu version 16
**----->
cmake --build _b…
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when i run a demo in systemctlm-cosim-demo and qemu, the problem is raise:
SystemC 2.3.2-Accellera --- Aug 4 2021 09:24:49
Copyright (c) 1996-2017 by all Contributors,
ALL RIGHTS…
heixi updated
3 years ago
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I would like to publish VHDL code (http://artutkia.com/?page_id=220) but this language is not supported.
Any plan fot this ?
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Hi
first thanks alot
second which feature of SATA Devices does your model Support?
Can you post a step by step guide for using your implementation and simulation.
My email is razi.marjani@gmail.com
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You have a great project here Sergey. I fixed a bug in my old version of River by switching SRLW from R Type ("ADD like") to I Type ("ADDI like"), and I just want to make sure you don't have the same …
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Hi! I'm trying to use this lib for some co-simulation works but I have some questions about its feasibility for my use case.
We have user logic based on XDMA and QDMA, but Xilinx's IP Core is encry…